Actel Corporation, Inc.

Microsemi Soc Corporation

Joel D Landry

William C Plants

Gregory William Bakker

Jonathan W Greene

Wenyi Feng

Suhail Zain

Randall Sexton

Sinan Kaptanoglu

John E McGowan

Warren K Miller

Tomek Jasionowski

Tomek P Jasinoski

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-of the K inputs.

FPGA logic cell with improved support for counters

A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

FPGA RAM blocks optimized for use as register files

A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.

Programmable delay line compensated for process, voltage, and temperature

A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the device. Provision is made for fourth instructions for saving a part of the internal logic state of the user logic programmed into the device into a non-volatile memory block and for fifth instructions for restoring a part of the internal logic state of the user logic programmed into the device from a non-volatile memory block. The device comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.

Programmable logic device with a microcontroller-based control system

A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.

Flash-based FPGA with secure reprogramming

A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device is disclosed. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the programmable logic integrated circuit device. Provision is made for fourth instructions for saving at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device into a non-volatile memory block and for fifth instructions for restoring at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device from a non-volatile memory block. The programmable logic integrated circuit device, comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.

A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.

Growing community of inventors

Colorado Springs, CO, United States of America

Joel D Landry