International Business Machines Corporation

Joel C Leininger

George P Taylor

Peter T Fairchild

Victor S Moore

Gordon J Robbins

Carlos Munoz-Bustamante

Jerry D Dixon

William L Stahl, Jr

Richard Eugene Birney

James W Davis

Richard N Ames

Dick K Hardin

Floyd R Bliss

A Level Sensitive Scan Design (LSSD) Shift Register Latch pair implemented in current switch logic is disclosed. The arrangement is characterized by the logic used to control the L1 and L2 latches being implemented in Differential Cascode Current Switch logic and the L1/L2 latches being coupled to only one current source. A 'merged' L1/L2 latch arrangement employing only one current source is provided for an LSSD testing environment.

Switch logic for shift register latch pair

Latch circuits implemented in multiple level Cascode Current Switch logic for performing various complex latch functions including Level Sensitive Scan Design (LSSD) testing and implementable in VLSI technology are described.

Latch circuits with differential cascode current switch logic

A microword control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microword control mechanism includes circuitry (15, 20) responsive to a processor instruction to be executed for providing an instruction dependent signal uniquely representative of such instruction. This microword control mechanism also includes sequence counter circuitry (18) for supplying a sequence of number signals. This microword control mechanism further includes a programmable logic array (17) responsive to the instruction dependent signal and to the sequence of number signals for producing a sequence of microwords needed to execute the processor instruction.

Microword control mechanism utilizing a programmable logic array and a

Binary logic structure is described which requires less space on an integrated circuit chip. This structure includes an encode programmable logic array responsive to a first group of binary input signals for producing a smaller number of binary signals which are encoded to identify different binary value combinations for the first group of binary input signals. This structure further includes a decode programmable logic array responsive to a second group of binary input signals and to the encoded binary signals produced by the encode programmable logic array for producing binary output signals representing logical functions of binary input signals in both the first and second groups. The chip space occupied by the encode programmable logic array is less than the additional chip space that would be required if the encode and decode programmable logic arrays were replaced by a single programmable logic array for receiving all the binary input signals in both the first and second groups. When used to provide microword generation apparatus for a microprogrammed digital system, the encode programmable logic array is responsive to a plural-bit system instruction for producing a plural-bit instruction identification signal uniquely representative of such system instruction but having a smaller number of bits than the system instruction. In such case, the decode programmable logic array is responsive to the instruction identification signal and to number signals produced by a sequence counter for producing a sequence of microwords needed to execute the system instruction.

Binary logic structure employing programmable logic arrays and useful in

A storage address link register system for enabling nested program branching wherein a first subroutine may call a second subroutine which is executed before the first subroutine returns program control back to the program which called it. The system includes a mechanism whereby the same set of storage address link registers may be used for nested branching both during the execution of a normal program and during the execution of an interrupt service program which breaks into the normal program and takes over control of the processor for a short interval of time. A mechanism is provided for saving the normal program values in the link registers at the commencement of the interrupt service program. A further mechanism is provided for monitoring the usage of the link registers by the interrupt program for enabling the normal program values to be restored in the link registers only after all interrupt program values have been removed from such link registers.

Link register storage and restore system for use in an instruction

An interrupt system for an instruction pre-fetch microprocessor is provided. The interrupt system includes an instruction address register coupled to a storage address register for holding the next succeeding instruction address to the pre-fetched in a sequence of instructions. A storage address register is provided and is coupled to the instruction address register and is coupled to the storage address register for holding the storage address to be accessed. A first latch receives and stores an interrupt request from one of a plurality of peripheral devices. A second latch, enabling interrupts, is coupled to the storage unit and controlled by instructions from the microprocessor. An interrupt link register stores values of the instruction address register and page information together with arithmetic and logic unit status bits when an interrupt request has occurred from one of the plurality of peripheral devices and an interrupt cycle is executed. The system further includes an interrupt circuit coupled to the first and second latches for inhibiting updating of the instruction address register to a next succeeding instruction. Circuitry is coupled to the first and second latches for inhibiting the operation of the interrupt circuitry following a data storage cycle or a successful branch operation. Circuitry is also provided to cause the next instruction to be executed following an interrupt cycle to be fetched from a predefined word in storage.

Instruction pre-fetch microprocessor interrupt system

In a data processing system, a mechanism provides independent assignment of page locations for a program's instructions and its data and better enables control to be transferred between programs, or portions thereof, that reside at different addresses in different pages of a multiple page instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return and Link instructions, each of which transfers control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.

Paging mechanism

A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.

Programmable control latch mechanism for a data processing system

An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.

Synchronous microcode generated interface for system of microcoded data

This carry save adder (CSA) utilizes a pair of edge-triggered flip-flops as output manifesting elements at each CSA bit position, one of these flip-flops being the 'sum trigger' which registers the half-sum value (herein called the 'sum bit'), and the other flip-flop of the pair being the 'carry trigger' which registers the carry value resulting from the binary addition performed by the CSA at that bit position. Each trigger has a latch portion for storing a sum or carry bit value that can be set or changed only at the leading edge of a clock pulse, being stable in the period between clock pulses. A latched sum or carry output bit value at any CSA bit position can be re-entered at any time as input to the same bit position or another CSA bit position, depending upon the operation to be performed (add, left or right shift, or complement). Each trigger also produces an unlatched output sum or carry value known as a 'presum' or 'precarry' bit. These unlatched bit values may be utilized for trial or test purposes, such as inputs to a lookahead logic network for determining whether a proposed complemental subtraction in a division operation can or cannot be successfully performed.

Carry save adder

A carry save adder (CSA) is adapted for use in dividing operations by providing it with a lookahead capability whereby it accurately predicts whether or not each of the proposed complemental subtractions in a division process could be successfully performed if actually attempted, and it actually performs only those subtractions that will not result in overdrafts. Each bit position of the carry save adder is arranged to receive sum, carry and data inputs and to furnish sum, carry, presum and precarry outputs. The sum and carry output bits are latched and remain undisturbed until the next complemental subtraction is performed. The presum and precarry bits are not latched and are fed into a lookahead logic network which analyzes the presum and precarry bit patterns derived from all of the CSA bit positions to determine rapidly by a logical trial procedure whether the divisor could be subtracted from the dividend or partial remainder value currently registered in the sum and carry latches of the CSA without causing an overdraft. While this trial procedure is in progress, the presum and precarry values may change without altering the latched sum and carry values. If the trial procedure indicates that a proposed complemental subtraction would be unsuccessful, then such subtraction will be skipped without actually being performed by the CSA, thus eliminating the necessity of determining whether overdrafts have occurred and correcting the overdrafts.

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Boca Raton, FL, United States of America

Joel C Leininger