Sematech, Inc.

Tokyo Electron Limited

Joel Barnett

Seung-Chul Song

David Gilmer

Chang Yong Kang

Paul Daniel Kirsch

Sangduk Park

Richard H Gaylord

Chanro Park

Byong Sun Ju

Richard James William Hill

A method for gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors is disclosed in various embodiments. According to one embodiment of the invention, a method is provided for processing a semiconductor substrate. The method includes providing a substrate containing a germanium-containing semiconductor or a compound semiconductor, and exposing the substrate to a process gas containing a sulfur-containing gas and a nitrogen-containing gas that passivates a surface of the germanium-containing semiconductor or the compound semiconductor with sulfur. According to another embodiment, the germanium-containing semiconductor or the compound semiconductor has an oxidized layer thereon and the exposing to the process gas removes the oxidized layer from the substrate. According to another embodiment, the substrate may be treated with hydrogen fluoride (HF) gas and ammonia (NH.sub.3) gas to remove the oxidized layer from the substrate before passivating the germanium-containing semiconductor or compound semiconductor with sulfur.

Gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors

The present invention includes methods directed to improved processes for producing a monolayer of sulfur on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element.

Ammonium sulfide passivation of semiconductors

Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Capacitors, systems, and methods

Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.

Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks

Growing community of inventors

Austin, TX, United States of America

Joel Barnett