Staktek Group L.p.

Dense-pac Microsystems, Inc.

Joel Andrew Mearig

John Patrick Sprint

Harlan R Isaak

Glen E Roeters

John A Forthun

Mark Chandler Calkins

Aaron Uri Levy

The present invention provides a plurality of vertically stacked semiconductor dies which are electrically connected to each other. Each semiconductor die has leads which extend out from at least two opposed side surfaces of the semiconductor die. Each lead defines a first junction, a second junction, an inner width and an outer width. The second junctions of the leads of the upper semiconductor die are electrically connected to the first junctions of the leads of the lower semiconductor die. Additionally, the inner widths of the leads of the upper semiconductor die prior to electrically connecting the leads of the upper and lower semiconductor dies are less than the outer widths of the leads of the lower semiconductor die.

Thin scale outline package

A method of making chip stacks begins with the formation of a plurality of panels having apertures therein and conductive pads on opposite sides thereof. Solder paste is deposited on the conductive pads prior to mounting plastic packaged IC chips within each of the apertures in each of the panels so that opposite leads thereof reside on the conductive pads at opposite sides of the apertures. The plural panels are then assembled into a stack, such as by use of a tooling jig which aligns the various panels and holds them together in compressed fashion. The assembled panel stack is heated so that the solder paste solders the leads of the packaged chips to the conductive pads and interfacing conductive pads of adjacent panels together, to form a panel stack comprised of a plurality of chip package stacks. Following cleaning of the panel stack to remove solder flux residue, the individual chip package stacks are separated from the panel stack by cutting and breaking the stack. Score lines across a topmost panel and transverse slots within remaining panels therebelow result in the formation of strips of chip package stacks when longitudinal cuts are made through the panel stack. The remaining portions of the uppermost panel within such strips are then snapped along the score lines thereof to separate the individual chip package stacks from the strips.

Modular panel stacking process

Growing community of inventors

Huntington Beach, CA, United States of America

Joel Andrew Mearig