Bitmicro Networks, Inc.

Bitmicro LLC

Joel Alonzo Baylon

Ricardo H Bruce

Elsbeth Lauren Tagayo Villapana

Rey H Bruce

Patrick Digamon Bugayong

Elsbeth Lauren T Villapana

The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Multilevel memory bus system

Multilevel memory bus system for solid-state mass storage

Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Multiple chip module and package stacking method for storage devices

Multiple chip module and package stacking for storage devices

Growing community of inventors

Cavite, Philippines

Joel Alonzo Baylon