International Business Machines Corporation

Joel Abraham Silberman

Sang Hoo Dhong

Osamu Takahashi

Balaram Sinharoy

Harm Peter Hofstee

Timothy Joseph Chainer

Pritish Ranjan Parida

Dieter F Wendel

Yu-Shiang Lin

Naoaki Aoki

Kevin John Nowka

James Douglas Warnock

Matthew R Wordeman

David Meltzer

Liang-Teck Pang

Evan G Colgan

Mark Delorman Schultz

Thomas J Brunschwiler

William Robert Reohr

Mary Douglass Brown

Gerd Schlottig

Chin Lee Ong

Stephen Douglas Posluszny

Arvind Raj Mahankali Sridhar

Dung Q Nguyen

Philip George Emma

Chung-Hsun Lin

Hung Cai Ngo

Jae-Joon Kim

Mohit Karve

Robert Allen Cordes

Maureen Anne Delaney

Jeffrey Herbert Fischer

Shih-Hsien Lo

Jafar Nahidi

Nobuo Kojima

Paula Kristine Coulman

Brian King Flachs

Chiaming Chai

James Wilson Bishop

Jeffrey Carl Brownscheidle

Hwa-Joon Oh

Jaehong Park

Robert J Bucki

Michael Thaithanh Phan

Steven Douglas Posluszny

Brian William Thompto

David William Boerstler

Silvia Melitta Mueller

Michael Richard Ouellette

James Norris Dieffenderfer

Joshua M Rubin

Jose Eduardo Moreira

Bruce Martin Fleischer

Thomas Philip Speier

Robert Allen Groves

Christopher Michael Abernathy

Francois Ibrahim Atallah

Xiaoxiong Gu

Uttam Shyamalindu Ghoshal

Michael Kevin Ciraula

Yong Liu

Michael Thomas Fragano

Saiful Islam

Sam G Chu

Jeffery Howard Oppold

Jeffrey L Burns

Toru Asano

Michael R Scheuermann

Bjorn P Christensen

Brian King Flacks

Neelesh Govindaraya Pai

Xiaomin Duan

Perng-Shyong Lin

Carmen C Sloan

Daniel Stephen Geise

Naoka Yano

Perng Shyong Lin

A cooling system includes a device to be cooled and a cooling device integrated with the device to be cooled. A cooling volume has cavities and active coolant flow controls configured to adjust coolant flow through the cavities. A reservoir is in fluid communication with the cavities and has a liquid outlet and an inlet for a gas or gas-liquid mixture. A two-phase coolant is in the reservoir and cavities. The two-phase coolant has a phase transition temperature between an ambient temperature and an expected device temperature. A capacitance sensor is configured to determine a coolant capacitance in the cavities. A control module is configured to determine a vapor quality and void fraction of the coolant based on the measured capacitance and to increase coolant flow if the determined vapor quality and void fraction indicate a dry-out condition. A secondary cooling line removes heat from the cooling device.

Active control for two-phase cooling

Methods and systems of matrix multiplication are described. In an example, a processor can multiply a first entry of a first vector of a first data array with a second vector of a second data array to generate a third vector of a third data array. The processor can store the third vector of the third data array in the second register file. The processor can multiply a second entry of the first vector with the second vector to generate a fourth vector of the third data array. The processor can store the fourth vector of the third data array in the second register file. The processor can combine vectors of the third data array that are stored in the second register file to produce the third data array.

Half-precision floating-point arrays at low overhead

Embodiments of the present invention include methods, systems, and computer program products for implementing instruction fusion after register rename. A computer-implemented method includes receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further performing a register rename within the instruction pipeline in response to the received plurality of instructions. The processor can further determine that two or more of the plurality of instructions can be fused after the register rename. The processor can further fuse the two or more instructions that can be fused based on the determination to create one or more fused instructions. The processor can further perform an execution stage within the instruction pipeline to execute the plurality of instructions, including the one or more fused instructions.

Instruction fusion after register rename

Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

Coalescing global completion table entries in an out-of-order processor

Methods and systems for implementing an instruction selection mechanism with class-dependent age-array are described. In an example, a system can include a processor that may sequence instructions. The system can further include a memory operatively coupled to the processor. The system can further include an array allocated on the memory. The array can be operable to store instruction age designations associated with a plurality of instructions sequenced by the processor. The array can be further operable to store the instruction age designations based on instruction classes. The processor can be operable to fetch an instruction from the memory. The processor can be operable to dispatch the instruction to a queue. The processor can be operable to store the instruction age designations associated with the instruction, in the array, based on an instruction class of the instruction.

Instruction selection mechanism with class-dependent age-array

Aspects of the invention include tracking relative ages of instructions in a first-in-first-out (FIFO) issue queue of an out-of-order (OoO) processor. The FIFO issue queue is configured to add instructions to the issue queue in a sequential order and to remove instructions from the issue queue in any order including a non-sequential order. The tracking of relative ages of instructions includes maintaining a head pointer to a location of an oldest instruction in the issue queue and a tail pointer to a location of a last instruction added to the issue queue. It is determined periodically whether the tail pointer is pointing to a location that includes a valid instruction. The tail pointer is updated to point to a previous sequential location in the issue queue based at least in part on determining that the tail pointer is not pointing to a location that corresponds to a valid instruction.

Head and tail pointer manipulation in a first-in-first-out issue queue

Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions in a group of instructions in the issue queue that were added to the issue queue prior to the instruction and that are not included in the threshold number of instructions that are tracked individually. A dependency between the instruction and the one or more other instructions in the group of instructions is tracked using a single summary bit that is set to indicate that a dependency exists between the instruction and the group of instructions. Instructions are issued from the issue queue based at least in part on the tracking.

Scalable dependency matrix with a single summary bit in an out-of-order processor

Aspects of the invention include tracking relative ages of instructions in an issue queue of an OoO processor. The tracking includes grouping entries in the issue queue into a pool of blocks, each block containing two or more entries that are configured to be allocated and deallocated as a single unit, each entry configured to store an instruction. Blocks are selected in any order from the pool of block for allocation. The selected blocks are allocated and the relative ages of the allocated blocks are tracked based at least in part on an order that the blocks are allocated. Each allocated block is configured as a first-in-first-out (FIFO) queue of entries, configured to add instructions to the block in a sequential order, and configured to remove instructions from the block in any order including a non-sequential order. The relative ages of instructions within each allocated block are tracked.

Block based allocation and deallocation of issue queue entries

Aspects of the invention include buffered instruction dispatching to an issue queue. A non-limiting example includes dispatching from a dispatch unit of a processor a first group of instructions selected from a first plurality of instructions to a first issue queue partition of the processor in a first cycle. A second group of instructions selected from the first plurality of instructions is passed to an issue queue buffer of the processor in the first cycle. The second group of instructions is passed from the issue queue buffer to the first issue queue partition in a second cycle. A third group of instructions selected from a second plurality of instructions is dispatched to a second issue queue partition in the second cycle.

Buffered instruction dispatching to an issue queue

Aspects include monitoring a number of instructions of a first type dispatched to a first shared port of an issue queue of a processor and determining whether the number of instructions of the first type dispatched to the first shared port exceeds a port selection threshold. An instruction of a third type is dispatched to a second shared port of the issue queue associated with a plurality of instructions of a second type based on determining that the number of instructions of the first type dispatched to the first shared port exceeds the port selection threshold. The instruction of the third type is dispatched to the first shared port of the issue queue associated with a plurality of instructions of the first type based on determining that the number of instructions of the first type dispatched to the first shared port does not exceed the port selection threshold.

Issue queue with dynamic shifting between ports

Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, tracking a specific dependency on each of a threshold number of instructions most recently added to the issue queue prior to the instruction, tracking as a single group a dependency of the instruction on any instructions in the issue queue that are not in the threshold number of instructions, and tracking for each source register used by the instruction an indicator of whether its content is dependent on results from an instruction in the single group that has not finished execution. Based at least in part on detecting removal from the issue queue of an instruction in the single group that has issued and not finished execution, the method includes indicating that the instruction is ready for issuance or waiting for a notification that the removed instruction has finished execution.

Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor

A structure for cooling an integrated circuit. The structure may include; an interposer cold plate having at least two expanding channels, each expanding channel having a flow direction from a channel inlet to a channel outlet, the flow direction having different directions for at least two of the at least two expanding channels, the channel inlet having an inlet width and the channel outlet having an outlet width, wherein the inlet width is less than the outlet width.

Counter-flow expanding channels for enhanced two-phase heat removal

Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor. The truncated via contacts allow for higher density via contact connections to the capacitor electrodes in regions which have a dense array of wiring of a single polarity, where interlevel via contacts cannot be utilized to provide contacts to the capacitor electrodes.

High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations

Aspects of the invention include detecting, in an out-of-order (OoO) processor, that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is the oldest group in an entry of a global completion table (GCT). It is determined that the entry in the GCT is a merged entry that is associated with both the first group of in-flight instructions and a second group of in-flight instructions dispatched immediately subsequent to the first group of in-flight instructions. The first group of in-flight instructions and the second group of in-flight instructions are completed in a single processor cycle. The completing is based at least in part on detecting that all instructions in the first group of in-flight instructions have a status of finished. The completing includes requesting release of resources utilized by both the first and second groups of in-flight instructions.

Completing coalesced global completion table entries in an out-of-order processor

Growing community of inventors

Somers, NY, United States of America

Joel Abraham Silberman