Siemens Industry, Inc.

Cirrus Logic Inc.

Joe White

Douglas F Pastorello

Jerome E Johnston

Robert C Bartmess

Juan Cabrera

A system and method is provided for qualitative analysis of baseband building automation networks. The system may include a processor configured to carry out a plurality of tests on a serial communication network that includes at least one field device that carries out building automation communications on the network. A first test may include: transmitting a series of queries for devices on the network, in which the queries are transmitted at incrementally lower transmission signal levels until message loss is detected; and determining a first lower signal level at which transmissions of queries occur without message loss on the network. In addition, the processor may be configured to determine and output on a display device at least one classification of the relative quality of the network with respect to at least one predetermined scale of relative network quality based at least in part on the first lower signal level.

System and method for qualitative analysis of baseband building automation networks

Isolated capacitance line voltage sensing is provided that avoids metal-to-metal contact for voltage sensing of a power signal present on a power wire. An external conductor is positioned by the power wire, creating a capacitor with the power wire conductor, insulation, and external conductor. The capacitance is used to measure the electric field, indicating a voltage level for the powered wire. The impedance mismatch caused by the capacitance is transformed. The impedance transformation circuit may be integrated with the external conductor, allowing voltage sensing by a voltage meter having a lower input impedance. A manual or automatic calibration circuit may be provided to ensure the measured voltage represents the actual voltage on the power wire.

Isolated capacitance line voltage sensor

A data clock pin SCLK may be used to receive an SCLK signal as well as sleep and reset signals. During normal operation, the SCLK input pin may receive the SCLK signal, a square wave type clock signal. However, the SCLK signal may also be coupled to a one-shot within the device. When signal SCLK is held high for a predetermined period of time, the one-shot is triggered and a SLEEP signal is generated. The device reacts to this SLEEP signal by entering a sleep mode. Similarly, if the SCLK signal is held low for a predetermined period of time, the one-shot may output a low level RESET signal. This RESET signal resets the device into an initial condition state. Other modes of operation, such as test modes and the like may be entered into by holding the SCLK signal high or low in conjunction with a predetermined logic level on another pin (e.g., VREF).

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Austin, TX, United States of America

Joe White