Motorola Corporation

Advanced Micro Devices Corporation

Legerity, Inc.

Sony Corporation

Joe W Peterson

James A McKenzie

David James Borland

Geoffrey E Brehmer

Dale E Gulick

Alfredo R Linz

Munehiro Yoshikawa

Roger A Whatley

Glen P Gilfeather

Shin Saito

Kazushige Tsurumi

Al Hartmann

Robert N Allgood

Masaru Nonogaki

Ken D Alton

Herchel A Vaughn

Hiroshi Matsubara

Toshiaki Iimura

Toshihiro Fujita

Geoffrey E Berhmer

Velayudhan V Nair

Bob Dildy

A computer system that functions as a cordless telephone base unit is disclosed. The computer system includes a cordless telephone device that can be operative through the computer system. The cordless telephone device can function as a cordless telephone base unit with the help of an external antenna that can be attached to the computer system housing. The cordless telephone device may, for example, include a cordless telephone card installed in one of a plurality of connector slots on the computer system motherboard. The cordless telephone device is coupled to a sound device, which may be a computer sound card and may also be installed on the computer system motherboard. The cordless telephone device comprises a cordless telephone base unit, a microphone output and a speaker input to allow the cordless telephone device to be coupled to the sound device in the computer system. An external cordless telephone handset is coupled to this cordless telephone device to allow a user to carry out a telephone communication over an external telephone line, which is connected to the sound device. The connection of the telephone line to the sound device also facilitates a telephone communication using the Internet. Thus, the computer unit will itself function as a cordless telephone base station. This will eliminate the need to have an external cordless telephone base unit.

Computer peripheral base station for a cordless telephone

The present invention comprises a telephone system and method that identify and announce the caller and/or the callee of an incoming telephone call. After receiving a telephone call from a caller, the telephone system answers the incoming telephone call. The identity of the caller is then determined. The telephone system prompts the caller to say his/her name. The name is recorded and repeatedly played back through a built-in speaker announcing the name of the caller to the users of the telephone. The telephone system may also ask the caller to say the name of the callee. In that case, the name of the callee is also recorded and repeatedly played back. The name of the caller and the name of the callee are both announced to the users of the telephone.

System and method for identifying and announcing a caller and a callee of an incoming telephone call

An electrical receptacle that provides dual-mode electric power through two separate sockets. The electrical receptacle includes a first socket configured to supply AC electric current at a high voltage (such as 120V or 240V AC) and a second socket configured to supply DC current at a low voltage current (such as 4V, 6V, or 12V DC). In one embodiment, the receptacle receives the high-voltage AC from electrical wiring in a building and generates the low-voltage DC. This embodiment of the receptacle has input terminals for receiving AC, mounting hardware, an AC-to-DC converter, and one or more DC output sockets. The receptacle may also have a standard AC output socket. The receptacle may be used to provide direct current at several different voltage levels. The different voltages may be accessed simultaneously through several different DC sockets. Alternatively or in combination, one or more switches may be used to select the voltage level delivered by individual sockets or groups of sockets. In another embodiment, the electrical receptacle receives the DC from an external source, such as 12 V DC supply lines installed in a building. In this embodiment, the electrical receptacle includes input terminals for the high-voltage AC, input terminals for the low-voltage DC, mounting hardware, at least one output socket for the AC, and at least one output socket for the DC. Additional switched or unstitched sockets may also be used. Also described is an electrical adapter that plugs into a standard electrical socket and generates low-voltage direct current.

Dual-mode AC/DC electrical receptacle

The present invention comprises an improved telephone system and method that enable a caller to leave a message on a telephone without the telephone first generating a ring sound. The telephone receives an incoming telephone call from a caller, and if the ring/message option feature is enabled, the telephone answers the incoming telephone call. The telephone answers the incoming telephone call prior to the telephone generating a ring sound. The caller is then given the choice by the telephone to either access an answering machine in order to leave a message or have the telephone generate a ring sound in order to alert the user or users to the incoming telephone call. If the caller chooses to leave a message, the telephone transfers control to an answering machine unit which plays a message requesting the caller to leave a message after the answering machine unit generates a characteristic tone. After the answering machine unit generates the characteristic tone, the answering machine unit receives and records a message from the caller. Thus, the caller may leave a message without disturbing the user. For example, the caller may call a telephone with the ring/message option feature and leave a message late at night when the user or users are asleep.

System and method for enabling a caller to selectively leave a message

A system for testing an overall system employing an integrated circuit with a modulator thereon is disclosed. The system for testing includes structure for causing the modulator to continually transmit data and structure for causing the continually transmitted data to exhibit extreme frequency deviation. In both instances the structure may be a single register. This register may also include a set of bits that may be set to select a continuous or an alternating pattern or, stated another way, a maximum or a minimum peak frequency deviation.

Self-contained self-testing data modulator

An intermediate frequency gain and rectifying stage for an IF system is implemented with a high swing folded-casecode structure terminated into a current-mirror load. The signal-path outputs are derived from the current-mirror loads, and the rectification and current-limiting RSSI functions are performed with two additional constant-current sources and two additional current-mirror loads. One load current from one leg or current path of the signal-path gain-stage is mirrored into a constant-current source and a second current-mirror structure. A second leg or current path of the signal-path gain-stage is likewise mirrored into yet another constant-current source and another current-mirror structure. When the input signal is not present, the load currents in the signal-path gain-stage are equal and the rectified output signal on an output node IOUT is constant or set to zero. With a differential input signal present, the load currents in the signal-path gain-stage produce a plus delta-current and minus delta-current. The plus delta-current, which represents a difference between the current in one of the legs of the signal-path gain-stage and the current of a corresponding constant current source, is mirrored to generate the RSSI current output signal at the IOUT node. Likewise, during the negative-half input-cycle the signal-path load currents are again mirrored and only the plus delta-load-current is rectified and output on the output node IOUT.

Intermediate frequency gain stage with rectifier

An IF receiver system includes an IF signal path formed by an IF amplifier section, a bandpass filter, and a limiter section. An RSSI (Receive Signal Strength Indicator) circuit is coupled to the IF amplifier section and the limiter section and generates an RSSI output signal which varies linearly with logrithmic changes in input power. A storage unit is coupled to the RSSI circuit and is configured to store a value which controls current limiting associated with the RSSI circuit. In one specific implementation, the limiter section includes a plurality of serially coupled limiter stages. The RSSI circuit includes a plurality of rectifying stages, wherein a separate rectifying stage is coupled to an input of a corresponding limiter stage. An additional rectifying stage is coupled to an output of a last of the limiting stages. The value within the storage unit controls the extent of current limiting associated with the additional rectifying stage.

Programmable intermediate frequency RSSI system including an adjustable

An I/O port interrupt mechanism includes a source register connected to the port for reporting sources of interrupts arising within the port, an interrupt mask register connected to the source register and operable to configure the I/O port for generation of interrupts, and an interrupt controller connected to the output of the source register and operable to hold off interrupts arising within the I/O port.

General I/O port interrupt mechanism

A transmitter for converting a binary digital signal into a pseudo-ternary signal at first and second output nodes (40, 41) to form differential output voltages includes a current source amplifier circuit (10), a first voltage source amplifier circuit (12) and a second voltage source amplifier circuit (14). The current source amplifier circuit (10) is responsive to a reference current for generating a first drive current and a second drive current. The first voltage source amplifier circuit (12) is responsive to a reference voltage, a first digital control signal, a second digital control signal and the first drive current for driving the first output node (40) to the reference voltage when the second digital control signal is at a high logic level and for driving the first output node (40) to a ground potential when the first digital control signal is at a high logic level. The second voltage source amplifier circuit (14) is responsive to the reference voltage, first digital control signal, second digital control signal, and second drive current for driving the second output node (41) to the reference voltage when the first digital control signal is at a high logic level and for driving the second output node (41) to the ground potential when the second digital control signal is at a high logic level. The transmitter has been designed so as to overcome the problem of line clamping during a power-down condition, provides a current limiting function, and reduces the ringing problem associated with driving an inductive load with a high impedance source.

Voltage source amplifier for use in a pseudoternary code transmitter

A digital-to-analog converter network for converting a digital signal having a plurality of binary bits into an analog output signal includes an R-2R ladder array (8a), a reference current source (IREF), a plurality of switches (S1, S2, . . . S9) associated with ladder sections of the ladder array (8a), and an operational amplifier (14). An equalization circuit (17) is operatively coupled to the inverting input of the operational amplifier (14) for selectively switching in a code-dependent impedance so that the effective output impedance of the ladder array (8a) remains substantially constant with binary codes of the digital input signal.

Digital-to-analog converter with no offset-induced errors

A transmitter for converting a binary digital signal into a pseudo-ternary signal. The transmitter has been designed so as to overcome the problem of line clamping during a power-down condition, provides a current limiting function, and reduces the ringing problem associated with driving an inductive load with a high impedance source.

Pseudo-ternary code transmitter

A protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a low impedance power supply bus structure and a plurality of bipolar and MOS clamping networks. The bipolar clamping networks are formed around each of the bonding pads for interlinking all of them together through the low impendance power supply bus structure. When any one of the bonding pads receives a higher voltage than a predetermined value and another remaining one of the bonding pads contacts a ground potential, current is routed from the one bonding pad through the low impedance power supply bus structure to the other bonding pad in order to discharge the same.

Protection system for CMOS integrated circuits

A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.

Recirculating MOS charge pump

An A/D system having a capacitive DAC is provided with a circuit for accurately testing the functionality of the A/D system. An accurate reference voltage which is associated with A/D systems is utilized directly by selectively coupling the accurate reference voltage to predetermined ones of a plurality of rank ordered capacitors forming a binarily weighted DAC via a plurality of switches. After charging the predetermined capacitors, an effective test voltage results which is then coupled by the switches to successive approximation circuitry associated with the A/D system. A resulting digital output code may be compared with the weighted analog value of the switched reference voltage to test whether the circuitry of the A/D system is functioning properly.

A/D Self-testing circuit

A fully differential gain stage having high gain and common-mode feedback is provided with minimal circuitry. Differential input transistors adapted to receive differential input voltages are coupled to load transistors. During a first time period, the gain stage is placed in unity gain and the load transistors are configured as diodes. Charge storage devices are charged during the first time period with a charge which is proportional to both the current of a current supply and the physical dimensions of the load transistors. During a second time period, the charge storage devices provide a bias voltage to the load transistors which maintains the common-mode output voltage at a predetermined value. During the second time period, the gain stage is configured for high gain operation.

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Austin, TX, United States of America

Joe W Peterson