Texas Instruments Corporation

Wolfspeed, Inc.

Joe W McPherson

Honglin Guo

Daniel Jenner Lichtenwalner

Ennis Takashi Ogawa

Sei-Hyung Ryu

Yaojian Leng

Brice McPherson

Edward Robert Van Brunt

Brian Goodlin

Thomas E Harrington, Iii

Brett Hull

Woongsun Kim

Naeem Islam

Shadi Sabri

Dongmei Lei

Thomas Dyer Bonifield

William R McKee

Anand Seshadri

Bryan David Sheffield

Robert Yung-Hsi Tsu

Robert L Pitts

Bob D Strong

Homi C Mogul

Roger Griesmer

Ajit Shanware

Matt N McCain

Anthony W Leigh

Gaddi S Haase

Kenan J Dickerson

Matthew N McCain

Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Power semiconductor devices including a trenched gate and methods of forming such devices

Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.

Power semiconductor device with reduced strain

The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.

Contact fuse which does not touch a metal layer

Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

Polysilicon structures resistant to laser anneal lightpipe waveguide effects

One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.

Capacitor-based method for determining and characterizing scribe seal integrity and integrity loss

In accordance with the invention, there are methods for transferring heat, for heating and cooling, and there is a solid state heat pump. The solid state heat pump can include a power supply that provides an electric field, a first metal layer, a dielectric layer disposed over the first metal layer, wherein the dielectric layer absorbs a first amount of heat upon application of the electric field and releases a second amount of heat upon alteration of the electric field, and wherein the second amount of heat is greater than the first amount of heat, and a second metal layer disposed over the dielectric layer. The alteration of the electric field can be achieved at least by one of reducing, removing, and/or reversing the polarity of the electric field. The solid state heat pump can also include a series resistor.

Solid state heat pump

One aspect of the invention provides an integrated circuit(IC) []. The IC comprises transistors [] and contact fuses []. The contact fuses each comprise a conducting layer [], a frustum-shaped contact [] has a narrower end that contacts the conducting layer and a first metal layer [] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [] that is located over and contacts the first metal layer.

Semiconductor device with improved contact fuse

One aspect of the invention provides an integrated circuit (IC). The IC comprises transistors and contact fuses. The contact fuses each comprise a conducting layer, a frustum-shaped contact has a narrower end that contacts the conducting layer and a first metal layer that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink that is located over and contacts the first metal layer.

An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layerorof FIGS.-), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer, andof FIGS.and) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (materialof FIGS.and) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.

Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer

Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure () within a semiconductor device (). The device typically comprises a first interconnect (), and a second interconnect (). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume () is determined, within which the primary structure is located. A buffer structure () is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.

Versatile system for diffusion limiting void formation

The present invention provides, in one aspect, a method of testing an electrical breakdown characteristic of a dielectric in a microelectronic device. This method includes determining a first dielectric breakdown voltage distribution of a first test sample by using a first voltage ramp rate, determining a second dielectric breakdown voltage distribution of a second test sample by using a second voltage ramp rate and determining a spacing distribution between conductive lines in the first and second test samples based on a field acceleration factor associated with the dielectrics of the first and second test samples, the first and second voltage ramp rates, and a difference between the first and second breakdown voltage distributions. This spacing distribution is used to determine corrected electric breakdown fields based on a measured breakdown voltage of a test sample, to improve microelectronic-device screening for interconnect dielectric reliability.

Dual ramp rate dielectric breakdown testing methodology

An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal,, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer,, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer,, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).

Growing community of inventors

Richmond, TX, United States of America

Joe W McPherson