Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Joe R Trogolo

Tathagata Chatterjee

Lily Springer

Dan M Mosher

David R Cotton

Cornelia H Blanton

Larry Latham

Jeff D Smith

Kenneth M Bell

Kaiyuan Chen

Henry Litzmann Edwards

Andrew Marshall

Pinghai Hao

Louis N Hutter

James Robert Todd

Imran Khan

Badih El-Kareh

Philipp Steinmann

Eric G Soenen

Hiroshi Yasuda

Sheldon Douglas Haynie

William C Loftin

Steve Merchant

William F Kyser, Jr

Bob Todd

Sameer P Pendharkar

Taylor R Efland

Fernando D Carvajal

Scott Balster

Jeffrey P Smith

Tathagata Chatterlee

Michael R Seacrist

A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Low noise JFET

The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) () includes a well region () of a first conductive type located within a substrate () and a gate region () of a second conductive type located within the well region (), the gate region () having a length and a width. This embodiment further includes a source region () and a drain region () of the first conductive type located within the substrate () in a spaced apart relation to the gate region () and a doped region () of the second conductive type located in the gate region () and extending along the width of the gate region (). In place of or addition to the doped region (), the high-voltage junction field effect transistor (JFET) () may includes a conductive field plate () located over and extending along the width of the gate region ().

Reliable high-voltage junction field effect transistor and method of manufacturing therefor

Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.

Silicide block isolated junction field effect transistor source, drain and gate

The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.

Open source/drain junction field effect transistor

Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure () and the required current density throughput of an electrical contact structure () are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Versatile system for optimizing current gain in bipolar transistor structures

Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.

Method to accurately estimate the source and drain resistance of a MOSFET

Reliable high-voltage junction field effect transistor and method of manufacture therefor

An interfacial oxide layer () is formed in the emitter regions of the NPN transistor () and the PNP transistor (). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor () to reduce the 1/f noise in the NPN transistor.

Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies

A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps

The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (), and an oxide region () overlapping the moat region. A double-diffusion region () is formed within the oxide region, having end cap regions () that are effectively deactivated utilizing geometric and implant manipulations.

System for high-precision double-diffused MOS transistors

A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.

Schottky diode with guard ring

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Plano, TX, United States of America

Joe R Trogolo