Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Hewlett-packard Development, L.p.

Joe Perry Cowan

Gary Belgrave Gostin

Debendra Das Sharma

John Alan Wickeraad

Sharon M Ebner

Larry N McMahan

Carl H Jackson

Renato John Recio

Frank R Dropps

Mark Edward Shaw

Gregory Francis Pfister

Derek Alan Sherlock

Jonathan Kent Ross

Michael R Krause

Richard W Adkisson

Craig William Warner

Dwight L Barron

Leith L Johnson

Michael Alex Schroeder

Mark W Bradley

Matthew B Lovell

Thierry Fevrier

Huai-Ter Victor Chong

Arad Rostampour

Kamran H Casim

David M Binford

Matthew B Hewlett-Packard Company Lovell

One aspect of the instant application can provide a networking device. The networking device can include a set of Compute Express Link (CXL) ports, a set of non-CXL ports, a set of bridge circuits associated with the set of CXL ports, and an interconnect. A respective bridge circuit can include a packet-conversion subcircuit to convert a CXL packet received at a corresponding CXL port to a customized packet and a protocol-conversion subcircuit to convert a CXL protocol to a customized protocol implemented by the networking device. The interconnect can switch customized packets among the CXL and non-CXL ports based on the customized protocol.

CXL fabric extensions

A system including a host and a device. The device has at least one non-prefetchable storage location. The host and the device are configured to map the at least one non-prefetchable storage location into memory mapped input/output space that is addressed via greater than 32 address bits.

Mapping non-prefetchable storage locations into memory mapped input/output space

A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

Communication among partitioned devices

A computing device having partitions, and a method of communicating between partitions, are disclosed wherein each partition comprises at least one address area readable but not writable from the other of the at least two partitions. In one embodiment one partition sends to the other partition a request for information, which information is in the other partition in an address area not accessible to the one partition, the other partition copies the information to an address area accessible to the one partition, and the one partition reads the information from the accessible address area. In another embodiment the at least one accessible address area of each partition includes a data area and a consumer pointer indicating the position to which that partition has read the data area in another partition.

Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.

Method and apparatus for direct input and output in a virtual machine environment containing a guest operating system

A distributed computer system includes a first subnet including a first group of endnodes, each endnode in the first group of endnodes having a unique destination location identification (DLID) within the first subnet. A second subnet in the distributed computer system includes a second group of endnodes, each endnode in the second group of endnodes having a unique DLID within the second subnet. A communication fabric is physically coupled to the first group of endnodes and the second group of endnodes. A partitioning mechanism associates a first partition key to every DLID in the first subnet for enabling communication between the first group of endnodes over the communication fabric. The partitioning mechanism associates a second partition key to every DLID in the second subnet for enabling communication between the second group of endnodes over the communication fabric.

Partitioning in distributed computer system

A bridge device for use in computer systems has a first interface to a first interconnect apparatus such as a processor bus. It also has a second interface to second interconnect apparatus such as an I/O bus. The second interconnect apparatus is of a type capable of connection to a DMA-capable peripheral device. The bridge device has address translation hardware to translate I/O virtual addresses received from the second interface into physical memory addresses for transmission onto the first interface. The address translation hardware has an associated coherency maintenance apparatus. In a particular embodiment, the address translation hardware has a translation lookaside buffer and the coherency maintenance apparatus is apparatus for snooping through the first interface, invalidating TLB entries when a page table in memory is updated.

Coherent memory mapping tables for host I/O bridge

A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In the coherent mode, the memory controller ensures that the data stored in system memory is accurately and precisely mirrored in all subservient copies of that data as might typically be stored in agent cache memories. Using, for example, a MESI type protocol, the memory controller limits access to memory so that only an &ldquo;owner&rdquo; or a particular portion or line of memory has write access and that, during the extension of these write privileges, no other agent has a valid copy of the data subject to being updated. Thus, the memory controller implements a first set of rule in the coherent mode of operation to insure that all copies of data stored by the agents are coherent with data stored in the memory. In a read current mode of access, a read-once segment of data is copied to an agent with the agent implementing a second set of rules to minimize or eliminate the possibility that the data might become stale prior to use or that it be misused by another agent or process. Thus, in the read current, an &ldquo;uncontrolled&rdquo; copy of the data is released subject to certain restrictions to be implemented by the receiving agent as defined by a second set of rules. For example, these rules require that the agent's copy of data be provided as an output and then invalidated within a predetermined period of time, that the agent have limit access to the memory during any set of fetch operations to no more than a predetermined maximum block size. Also included is a requirement that the copy of data include only that data contained within a range of memory addresses, the range beginning within a predetermined block of memory addresses and continuing through an end of block address. These limitations limit the amount of data that might be subject to misuse, particularly in the case of a failure resulting in the inability of a requesting agent to complete a transaction according to the rules.

Using read current transactions for improved performance in directory-based coherent I/O systems

A snapshot mechanism that includes an apparatus and method for tracking DMA read requests for cacheable data that can be altered before the data is returned to a requesting I/O device is herein disclosed. Attributes that uniquely identify the original I/O device and DMA read request are stored in a cache tag unit. A read lock is set when a request is made to obtain the requested data when it is not resident in a local cache. When the cache line containing the requested data is snooped out and the read lock is set, then the cache line is set in a snapshot state. The snapshot state assures that only the original I/O device receives the read data when it has been altered subsequent to the time the original DMA read request was made. Once the data is returned to the original I/O device, the cache line is invalidated in order to prevent another I/O device from reading the stale data. Prefetched data is marked as such and cannot be marked as snapshot data.

Apparatus and method for ensuring forward progress in coherent I/O systems

Growing community of inventors

Fort Collins, CO, United States of America

Joe Perry Cowan