Freescale Semiconductor,inc.

Motorola Corporation

Joe Mogab

Bich-Yen Nguyen

Mariam G Sadaka

Chun-Li Liu

Philip J Tobin

Rama I Hegde

Kenneth H Smith

Tushar Praful Merchant

James R Wasson

Gregory S Spencer

Pawitter Jit Mangat

Christopher C Hobbs

David Gilmer

Hsing H Tseng

Leonard John Borucki

Melissa O Zavala

Debby Eades

A semiconductor process and apparatus provide a high performance CMOS devices () with hybrid or dual substrates by etching a deposited oxide layer () using inverse slope isolation techniques to form tapered isolation regions () and expose underlying semiconductor layers () in a bulk wafer structure prior to epitaxially growing the first and second substrates () having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes () over a first substrate () that is formed by epitaxially growing (100) silicon and forming second gate electrodes () over a second substrate () that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Inverse slope isolation and dual surface orientation integration

A stencil mask ( or ) has both a thin membrane layer ( ) and a stress controlled layer ( ) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer ( ) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer ( ) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics ( ) onto resist ( ) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.

Method for fabricating a thin-membrane stencil mask and method for making a semiconductor device using the same

A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Transistor with layered high-K gate dielectric and method therefor

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Austin, TX, United States of America

Joe Mogab