International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Joe Martin Poss

Earl Albert Cunningham

Jerome Thomas Coffey

Dale E Goodman

Richard Leo Galbraith

Timothy Joseph Schmerbeck

Peter John Windler

Robert Andrew Kertis

David James Stanek

Jodie Ann Christner

Gregory J Kerwin

Tri C Nguyen

An electronic device incorporates a linear voltage regulator circuit which includes an external pass transistor that does not rely on internal compensation, provides high gain, and exhibits reduce silicon area and power requirements. Circuits according to the present invention provide sufficient bandwidth with an error amplifier and drive capability to keep any secondary poles sufficiently far from the unity gain bandwidth (UGB) while maintaining good power supply rejection.

Efficient low dropout linear regulator

A linear voltage regulator circuit includes an external pass transistor that does not rely on internal compensation, provides high gain, and exhibits reduce silicon area and power requirements. Circuits according to the present invention provide sufficient bandwidth with an error amplifier and drive capability to keep any secondary poles sufficiently far from the unity gain bandwidth (UGB) while maintaining good power supply rejection.

An input driver for use with a differential folder in a flash A/D converter having a static ladder that provides an array of reference voltages and a method of operation thereof. The input driver includes a differential signal driver, coupled to an AC input signal, that generates first and second complementary drive signals for a differential folder stage. A tracking circuit, coupled to the differential signal driver, is utilized to maintain a voltage at the center of the static ladder to improve common mode rejection of the input driver without reducing bandwidth. In a related embodiment, the voltage at the center of the static ladder is an average DC voltage of the first and second drive signals.

Input driver for a differential folder employing a static reference ladder

A combined read and write VCO for data channels is disclosed. The combined read and write VCO for data channels shares a common loop capacitor while providing optimal read and write VCO loop responses, and allows the VCO to relock to the write timebase after a read very quickly while maintaining an accurate timebase. The combined read and write VCO includes an oscillator providing an output signal having a frequency that varies proportionately to an oscillator input signal and an adjustable voltage source, the adjustable voltage source having a first configuration for a write mode and a second configuration for a read mode, and the adjustable voltage source providing the oscillator input signal to the oscillator in response to receiving an input current signal. The adjustable voltage source includes a first and second capacitor coupled in series and a switch coupled across the second capacitor, the switch being open to provide the first configuration and closed to provide the second configuration. The oscillator further includes a transconductance amplifier for receiving the input signal from the adjustable voltage source and converting the input signal to a current signal having a first current value, a current modifier, the current modifier providing a current phase signal according to whether a write or a read mode is selected and whether an acquisition or track mode is selected, an adder, coupled to the transconductance amplifier and the current modifier, the adder modifying the current signal according to the current phase signal to produce an adjusted current signal and a current controlled oscillator, coupled to the adder, the current controlled oscillator receiving the adjusted current signal and producing an output signal having a frequency proportional to a magnitude of the current of the adjusted current signal.

Combined read and write VCO for DASD PRML channels

A high speed analog timing and gain feedback control methods and a low power analog tracking timing and gain feedback apparatus are provided for data detection, such as, partial-response maximum-likelihood (PRML) data detection in a direct access storage device (DASD). The interleaved gain and timing tracking control circuit includes an even interleave gain and timing tracking control providing an even interleave gain error signal and an even interleave timing error signal; and an odd interleave gain and timing tracking control providing an odd interleave gain error signal and an odd interleave timing error signal. The even interleave gain error signal and the odd interleave gain error signal are combined to provide a resulting gain control signal. The even interleave timing error signal and the odd interleave timing error signal are combined to provide a resulting timing control signal. The resulting gain control signal is applied to a variable gain amplifier and the resulting timing control signal is applied to a variable clock circuit in a data channel of a direct access storage device (DASD).

Interleaved analog tracking timing and gain feedback loops for partial

A target specific folded analog to digital converter (ADC) is provided, such as for use in a data detection channel in a direct access storage device (DASD). The high speed analog to digital converter (ADC) includes a digital signal decoder for decoding specific target levels of an analog signal. An analog to digital converter section of the ADC converts an analog error signal of the analog signal to digital decoder outputs representing the analog error signal.

Target specific folded analog to digital converter for direct access

A Class IV Partial Response Maximum Likelihood data channel for analog signal processing of a disk drive signal in tracking mode includes a signal error generating circuit for 'folding' the analog disk drive signal around the three PR-IV target values of +1, -1 and 0. Using the smaller error signal rather than the larger analog disk drive signal by which the disk drive signal deviates from the target values results in significant power saving with no reduction in electronic signal to noise ratio. An integrated error generating circuit generates both a gain error signal and a timing error signal from the folded error signal for feedback control of the data channel variable gain amplifier and variable clock oscillator. Shared processing of the timing and gain error signals results in power savings and simpler circuitry.

Signal processing circuit with feedback extracted from a sampled analog

Analog signal processing circuit with integrated gain and timing error

Signal error generating circuit for an analog signal processing channel

A direct access storage device includes at least one disk mounted for rotation about an axis and having opposed disk surfaces for storing data. A magneto-resistive (MR) transducer head is mounted for movement across each respective disk surface for writing to and for reading data signals from the disk surface. Each MR transducer head includes a write element and a read element. A preamplifier, associated with the MR transducer head, amplifies read and write signals of the read element and the write element. A flex cable couples the read and write signals between the preamplifier and the MR transducer heads. The flex cable includes a common read return signal line for each sequential pair of the MR transducer heads.

Direct access storage device with magneto-resistive transducing head

A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders with a positive phase voltage source connected at the top and bottom of one of the pair of series connected resistor ladders and a negative phase voltage source connected at the top and bottom of the other one of the pair of series connected resistor ladders; both the positive phase voltage source and the negative phase voltage source including a predetermined first DC voltage value. At least one additional positive phase voltage source is connected to the one of the pair of series connected resistor ladders and at least one additional negative phase voltage source is connected to the other one of the pair of series connected resistor ladders. The additional positive phase and negative phase voltage sources include a predetermined second DC voltage value.

Split flash analog to digital converter differential driver

A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders. A positive phase and negative phase emitter follower transistor pair is connected to the pair of series connected resistor ladders. The positive phase and negative phase emitter follower transistor has a collector connected to a supply voltage and has an emitter coupled to a respective one of the pair of series connected resistor ladders. A respective positive phase and negative phase AC current source drives the base of the respective positive phase and negative phase emitter follower transistor. A reference DC current source is coupled to the base of the positive phase and negative phase emitter follower transistors for determining a range of the ADC. A current source transistor pair biases the emitter follower transistor pair. A first transistor of the current source transistor pair supplies current to the positive phase emitter follower transistor and a second transistor of the current source transistor pair supplies current to the negative phase emitter follower transistor. The first transistor has a control node capacitively coupled to the emitter of the negative phase emitter follower transistor and the second transistor having a control node capacitively coupled to the emitter of the positive phase emitter follower transistor.

Current boost for differential flash analog to digital converter driver

Apparatus and method of data recovery are provided for data detection in a partial-response (PR) data channel. The PR data channel includes an analog-to-digital converter (ADC) for providing digital samples of a readback data signal and a voltage controlled oscillator (VCO) timing control coupled to the ADC. A data recovery procedure (DRP) is established responsive to a detected readback error. Using amplitude offset circuitry, amplitude of the readback data signal is selectively adjusted responsive to the detected readback error; and using gain control, a correction current applied to the VCO timing control is changed responsive to the detected readback error.

Data recovery procedure using DC offset and gain control for timing loop

A method and apparatus is disclosed for adaptively controlling the biasing current applied to magnetoresistive (MR) read heads within a magnetic disk drive to provide optimized bias for each head/disk/channel component combination. An optimized bias current for each head is ascertained and stored on the disk surface at the time of manufacture. During each power up operation the values are transferred to random access memory which is accessed during the execution of each head switch command to apply bias current in accordance with the optimized value to the active MR head. Periodic reoptimization and updating of the stored values is effected by general error measurement circuitry that forms a part of the device control system and is invoked to perform the reoptimization upon the occurrence of an event such as a predetermined duration of power on operation subsequent to the last reoptimization procedure.

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Rochester, MN, United States of America

Joe Martin Poss