Asm IP Holding B.v.

Applied Materials, Inc.

Asm IP Holdings B.v.

Joe Margetis

John Tolle

Nupur Bhargava

Junwei Su

David Kohen

Amir Kajbafvala

Gregory Michael Bartlett

Sonti Sreeram

Xin Sun

Qi Xie

Dieter Pierreux

Patricia M Liu

Xuebin Li

Tomohiko Kitajima

Matthew G Goodman

Gill Yong Lee

Robert Michael Vyne

Rami Khazaka

Caleb Miskin

Lucas Petersen Barbosa Lima

Peter Westrom

Sathya Chary

Yanfu Lu

Abdul Wahab Mohammed

Yen Lin Leow

Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

Reduced strain Si/SiGe heteroepitaxy stacks for 3D DRAM

Embodiments of the present invention generally relate to methods of epitaxially growing boron-containing structures. In an embodiment, a method of depositing a structure comprising boron and a Group IV element on a substrate is provided. The method includes heating the substrate at a temperature of about 300° C. or more within a chamber, the substrate having a dielectric material and a single crystal formed thereon. The method further includes flowing a first process gas and a second process gas into the chamber, wherein: the first process gas comprises at least one boron-containing gas comprising a haloborane; and the second process gas comprises at least one Group IV element-containing gas. The method further includes exposing the substrate to the first and second process gases to epitaxially and selectively deposit the structure comprising boron and the Group IV element on the single crystal.

Epitaxial methods including a haloborane formula for growing boron-containing structures having increased boron concentrations

Methods and devices for epitaxially growing boron- and gallium-doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

Method for depositing boron and gallium containing silicon germanium layers

A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

Method for depositing a Group IV semiconductor and related semiconductor device structures

A method of forming a silicon germanium layer on a surface of a substrate and a system for forming a silicon germanium layer are disclosed. Examples of the disclosure provide a method that includes providing a plurality of growth precursors to control and/or promote parasitic gas-phase and surface reactions, such that greater control of the film (e.g., thickness and/or composition) uniformity can be realized.

Methods for silicon germanium uniformity control using multiple precursors

Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.

Methods of forming structures including silicon germanium and silicon layers, devices formed using the methods, and systems for performing the methods

A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation

Method for depositing a group IV semiconductor and related semiconductor device structures

A flange, flange assembly, and reactor system including the flange and flange assembly are disclosed. An exemplary flange assembly includes heated and cooled sections to independently control temperatures of sections of the flange. Methods of using the flange, flange assembly and reactor system are also disclosed.

Temperature-controlled flange and reactor system including same

A method for selectively depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The method may further include, exposing the substrate to at least one Group IV precursor, and exposing the substrate to at least one Group IIIA halide dopant precursor. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

Method for selectively depositing a Group IV semiconductor and related semiconductor device structures

A method for depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include: providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include: exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA dopant precursor; wherein the at least one Group IIIA dopant precursor comprises a borohydride, an organic borohydride, a halide, or an organohalide. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

A method for forming a forming a silicon germanium tin (SiGeSn) layer is disclosed. The method may include, providing a substrate within a reaction chamber, exposing the substrate to a pre-deposition precursor pulse, which comprises tin tetrachloride (SnCl), exposing the substrate to a deposition precursor gas mixture comprising a hydrogenated silicon source, germane (GeH), and tin tetrachloride (SnCl), and depositing the silicon germanium tin (SiGeSn) layer over a surface of the substrate. Semiconductor device structures including a silicon germanium tin (SiGeSn) layer formed by the methods of the disclosure are also provided.

Methods for forming a silicon germanium tin layer and related semiconductor device structures

A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950&#xb0; C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3&#xd7;10atoms per cubic centimeter.

Growing community of inventors

Gilbert, AZ, United States of America

Joe Margetis