Advanced Micro Devices Corporation

Joe J Sargunaraj

Vydhyanathan Kalyanasundharam

Ganesh Balakrishnan

Chintan S Patel

Alexander J Branover

Christopher Jude Brennan

Ravindra Nath Bhargava

Akshay Lahiry

Girish Balaiah Aswathaiya

The disclosed computer-implemented method includes detecting a low utilization time period for memory traffic between a cache and memory, selecting from the cache, in response to detecting the low utilization time period, a dirty cache entry based on one or more factors, and writing the dirty cache entry back to the memory during the low utilization time period. Various other methods, systems, and computer-readable media are also disclosed.

Dynamically controlled cache rinsing

A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

Mechanism to efficiently rinse memory-side cache of dirty data

Growing community of inventors

Santa Clara, CA, United States of America

Joe J Sargunaraj