Texas Instruments Corporation

Joe G Tran

Jiong-Ping Lu

Freidoon Mehrad

Shaofeng Yu

Yaw S Obeng

Ping Jiang

Brian Keith Kirkpatrick

Steven Arthur Vitale

Gregory Boyd Shinn

Alfred J Griffin, Jr

Shawn T Walsh

James B Friedmann

Wayne A Bather

Ju-Ai Ruan

Michelle L Hartsell

Troy A Yocum

Jaideep Mavoori

Somit Joshi

John E Campbell

Chad J Kaneshige

Michael J McGranaghan

Andrew Brian Nelson

Janice D Makos

Arun Sivasothy

Richard A Stice

Freidoon Mehard

Shafoeng Yu

A method of filling STI trenches with dielectric with reduced particle formation. A method of depositing unbiased STI oxide on an integrated circuit during STI trench fill that reduces STI defects during STI CMP.

Method to reduce particles during STI fill and reduce CMP scratches

A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device

A system () removes wafer edge residue from a target wafer (). A wafer holding mechanism () holds and rotates the target wafer (). A residue remover mechanism () mechanically interacts or abrades an edge surface of the target wafer () and removes strongly adhered residue from the edge surface of the target wafer (). The residue remover mechanism () controls coverage of the mechanical interaction and magnitude of the mechanical interaction.

Systems and methods for removing wafer edge residue and debris using a residue remover mechanism

A method for making a transistorthat includes using a transition metal nitride layerand/or a SOG layerto protect the source/drain regionsfrom silicidation during the silicidation of the gate electrode. The SOG layeris planarized to expose the transition metal nitride layeror the gate electrodebefore the gate silicidation process. If a transition metal nitride layeris used, then it is removed from the top of the gate electrodebefore the full silicidation of the gate electrode

FUSI integration method using SOG as a sacrificial planarization layer

Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device

The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer materialover gate electrodesthat are, in turn, located over a microelectronics substrate. The gate electrodeshave a doped regionlocated between them. A portion of the spacer materialis removed with a chemical/mechanical process using a slurry that is selective to a portion of the spacer material. The method further comprises etching a remaining portion of the spacer materialto form spacer sidewallson the gate electrodes. The etching exposes a surface of the gate electrodesand leaves a portion of the spacer materialover the doped region. Metal is then incorporated into the gate electrodesto form silicided gate electrodes

Method to obtain fully silicided poly gate

The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layerover gate structureslocated over a microelectronics substratewherein the gate structuresinclude sidewall spacersand have a doped regionlocated between them. A protective layeris placed over the capping layerand the doped region, and a portion of the protective layerand capping layerthat are located over the gate structures are removed to expose a top surface of the gate structures. A remaining portion of the protective layerand capping layerremains over the doped region. With the top surface of the gate structuresexposed, metal is incorporated into the gate structures to form gate electrodes

A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.

Chemical mechanical polishing method and apparatus

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

Growing community of inventors

Irving, TX, United States of America

Joe G Tran