Semiconductor Components Industries, LLC

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Joe Fulton

Zia Hossain

Mohamed Imam

Evgueniy Nikolov Stefanov

Chun-Li Liu

Mohammed Tanvir Quddus

Taku Yamamoto

Yoshio Enosawa

Katsuya Yamazaki

Masami Tanaka

Prasad Venkatraman

Ali Salih

Jefferson W Hall

Peter Moens

Stephen St Germain

Balaji Padmanabhan

Mihir Mudholkar

Woochul Jeon

Alexander Young

Jason McDonald

Philip Celaya

A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Half-bridge HEMT circuit and an electronic package including the circuit

A circuit can include a transistor coupled to a resistor or a diode. In an embodiment, the circuit can include a pair of transistors arranged in a cascode configuration, and each of the transistors can have a corresponding component connected in parallel. In a particular embodiment, the components can be resistors, and in another particular, embodiment, the components can be diodes. The circuit can have less on-state resistance as compared to a circuit in which only one of the components is used, and reduces the off-state voltage on the gate of a high-side transistor. An integrated circuit can include a high electron mobility transistor structure and a resistor, a diode, a pair of resistors, or a pair of diodes.

Circuit and an integrated circuit including a transistor and another component coupled thereto

A structure for making a LDMOS transistor () includes an interdigitated source finger () and a drain finger () on a substrate (). Termination regions () are formed at the tips of the source finger and drain finger. A drain () of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region () of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance

LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance

A high voltage MOSFET device ( ) has an nwell region ( ) with a p-top layer ( ) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability

A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion and merge together into a single channel region. The resulting channel region has a dopant concentration that is less than the dopant concentrations of the individual HV regions. The compact MOS device exhibits a low threshold voltage characteristic.

Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same

A high voltage MOSFET device ( ) has a well region ( ) with two areas. The first area ( ) has a high dopant concentration and the second area ( ) has a low dopant concentration. Inside the well region a region of a secondary conductivity type ( ) is formed. The second area ( ) is typically underlying a gate region ( ). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the &ldquo;on&rdquo; state. The MOSFET device further has a p-top layer ( ) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.

Method for manufacturing a high voltage MOSFET device with reduced on-resistance

A high voltage MOS device ( ) is disclosed. The MOS device comprises an n-well region ( ) with two areas. The first area ( ) has a high dopant concentration and the second area ( ) has a low dopant concentration. Inside the well region a region of a secondary conductivity type ( ) is formed. The second area ( ) is typically underlying a gate ( ). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the &ldquo;on&rdquo; state.

High voltage metal oxide device with enhanced well region

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Chandler, AZ, United States of America

Joe Fulton