International Business Machines Corporation

Joe C St Clair

Alexander K Spencer

Robert L Mansfield

Steven P Larky

Marc Segre

Leon Lumelsky

Alan W Peevers

Satish Gupta

James D Wagoner

Hector G Romero, Jr

Steven Mark Thurber

John Michael Kaiser

Ronald John Bowater

Paolo Sidoli

Paolo G Sidoli

Deborah D Brase

A method and system for sequentially addressing multiple components, having a limited number of externally available address lines, on a communication bus. The method and system employs an addressing scheme in combination with a specific interconnection of the components. This combination enables each of the components to be addressed in a sequential fashion by dynamically altering their address. Thus, allowing a virtually unlimited number of components to be coupled to the communication bus without the traditional concerns over the number of externally available address lines.

Method and system for addressing multiple components on a communication

An information handling system includes one or more processors, a system bus or network connecting the processors, a memory system connected to the system bus, an asynchronous signal controller connected to the system bus, one or more I/O bridges connected to the system bus, an I/O bus connected to each I/O bridge, one or more devices connected to the I/O bus, including perhaps another I/O-bus-to-I/O-bus bridge where additional devices may be connected to a second I/O bus, wherein the first or host bridge includes remote interrupt control logic having a register wherein an input to each position in the register is from one of the I/O devices downstream from the host bridge, and a shadow register address buffer, both under the control of a sample circuit connected to outputs of the register such that when a change in any register position is detected by the sample circuit, the entire contents of the register are sent to the shadow register indicated in the shadow register address buffer by a processor bypass technique such as the well known direct memory access technique.

Information handling system for transmitting contents of line register

Apparatus and methods for picking three dimensional objects from images depicted on a video display. The displayed objects are selectively rerendered. During such rerendering the object pixels are compared in depth to the data in a Z buffer for determining visibility. The number and size of the objects subject to rerendering by the rasterization processor is constrained by using the front end graphics processor to define object extents and by rerendering only extents which have been clipped to the boundaries of the pick window. The rerendering operation does not alter the three dimensional graphics image stored in and repetitively scanned from the frame buffer. Selection between multiple objects within the pick window can include a weighted comparison using a pick plane memory to store visibility data by object.

Apparatus and method for relating a point of selection to an object in a

A pixel-depth converter for source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth. A packed-pixel-data depacker circuit receives source-pixel data words having a packed-pixel data format from a source-pixel-data memory and transmits the data words depacked-pixel-data-word-component-by-depacked-pixel-data-word-component in accordance with a user selected pixel-depth-conversion scale factor. A pixel-data-conversion-table storage circuit stores selectable depth-altering pixel-data-conversion data in locations having conversion-table read addresses which are associated with values corresponding to the selected pixel-depth-conversion scale factor. The storage circuit includes independently-operable converted-data-read parallel output ports and associated conversion-table read-address input ports. Conversion-lookup addresses may be applied independently in parallel to the plurality of conversion-table storage circuit. Stored conversion data can be read in parallel from the associated converted-data-read output ports. Input ports of multiplexers are connected to corresponding terminal subsets of the depacker circuit which are associated with different pixel-depth-conversion scale factor. A conversion-lookup address output port of each multiplexer is connected to an associated read-address input port of the storage circuit. The multiplexer control-signal input ports are connectable to a bus for receiving a scale-factor-selection signal which specifies the desired pixel-depth-conversion scale factor and corresponding depacked-source-pixel-data portions.

Pixel depth converter for a computer video display

A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.

Flexible dynamic memory controller

A communication system for providing a communication path between two of a plurality of devices. A first port is provided that is connected to at least one device. A second port is provided connected to a second device. A switch is provided connecting the two ports for communications connection between the ports in response to commands form the devices to each other. The switch includes the capability to monitor communications between the devices and to determine when a change is to be made in the communications path and then to make the change accordingly.

Third party evavesdropping for bus control

A display control such as a virtual display adapter allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory. This large area of memory includes system memory, and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.

Virtual display adapter

A processing system is provided that includes an external device connected to a processor. The external device has the capability of responding to external device commands wherein each of these external device commands is performed within at least one fixed time cycle. The processor provides these external device commands and, further, includes the means for executing instructions that not only specify the external device commands but also specify at least one internal command to be performed by the processor simultaneously with the performance of the external device command and within the same fixed time cycle. In the disclosed embodiment, a graphics display system is provided that includes a system processor, a graphic processor, a graphics memory and a display device. The graphics processor receives instructions from the system processor which specifies commands to be executed by both the graphics processor and the graphics memory. Each graphics memory command is executed within a fixed time cycle simultaneously with the execution of a corresponding graphics processor command executed within the graphics processor.

Graphics function controller for a high performance video display system

A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.

High resolution graphics display adapter

In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter is performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a first predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reacing to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms. This counter circuit capability increases the speed at which line draw functions and bit block transfer functions can be accomplished in a graphics display system processor.

Graphics display system function circuit

A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality 'antialiased' text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the 'burst' mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

Pixel data path for high performance raster displays with

A graphics display system including a circuit that receives graphics information to be displayed and a memory that stores the graphics information in a memory array that includes a portion that directly corresponds to the image area for display. The memory provides a single access operation to the array during a single memory cycle. Circuitry is provided that is connected to the receiving means and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle (wherein N and M are integers each greater than one). A display is connected to the memory that displays the graphics information contained in the image area array portion of the memory. The graphics display system further includes the capability to provide a patterned line intersection where the continuity of the line pattern is maintained along the intersection of the lines.

Graphics display system with memory array access

A counter is used to concurrently refresh a video display and a memory associated with such video display. Address bits are output from the counter to the sync decode logic used to refresh the display as well as to multiplexing means connected to the associated memory. The multiplexing means has three pairs of inputs. The first pair of inputs comprises refresh addresses from the counter for refreshing the memory array. The second pair of inputs to the multiplexing means comprises memory update addresses for writing new information into the memory. A third pair of inputs to the multiplexing means performs two functions. The first function enables the multiplexing means to output either the update addresses or the refresh addresses depending on the state of such inputs. The second function of the third pair of inputs is to identify the output of said multiplexing means as either a row address or a column address to the associated memory. The apparatus and technique disclosed herein is especially pertinent when a 'nibble mode' dynamic RAM is used as the memory.

Growing community of inventors

Round Rock, TX, United States of America

Joe C St Clair