Hewlett-packard Development Company, L.P.

Micron Technology Incorporated

Joe Bolding

Dan Tormey

Daniel G Tormey

Gerald Everett

Tony M Brewer

Dean E Walker

John D Leidel

Kevin R Wadleigh

Janis Delmonte

Matt Jacunski

Ron Gilbert, Jr

Bjorn Helgaas

Alexander Chiang

Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride are disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated. For example, one or more bit of the instruction payload may be designated as a context switch bit (CTX) for expressly controlling context switching.

Systems and methods for selectively controlling multithreaded execution of executable code segments

Embodiments include methods, apparatus, and systems for controlling multiple simulations. One embodiment is a method that includes executing plural architectural simulators being interconnected to form a platform for hardware simulation; placing at least one of the plural architectural simulators into a pause state; and automatically minimizing windows associated with the at least one of the plural architectural simulators.

Method and apparatus for controlling multiple simulations

In one embodiment, a method for evaluating code usage includes monitoring instructions executed by a processor, counting instances of execution of each instruction, correlating the executed instructions with source code instructions, and providing an indication of source code usage to a user.

Systems and methods for evaluating code usage

A system and method for increasing performance in a simulator environment operable to simulate a multiprocessor platform with program code running thereon. A set of processors are initialized upon instantiating the simulator environment on a host machine for executing the program code instructions. Code execution on a simulated processor is suspended by executing a simulator API routine which is called when the program code is to enter an idle state. The host resources that would otherwise have been spent on the processor running the idle loops are therefore conserved for use by the remaining processors.

System and method for increasing performance in multi-CPU simulation

A system that indexes text according to an arbitrary set of indices and automatically generates hyperlinks from each index to a related subject in a document. A text file containing the documentation of interest is used as input to a hyperlink processing program that generates a file containing links to all of the topics of interest. A category file is then created that indicates an association between each of the topics and corresponding subjects included in each topic. Next, a data structure is generated that associates each topic with corresponding subject names. A plurality of subject name files is generated, each including HTML (hypertext markup language) text corresponding to an associated subject, and a file comprising said hyperlinks to each of the subject name files is generated. A plurality of index files is generated, each including hyperlinks between each of the topics and corresponding subject name files. A list of category names corresponding to a primary set of indices is displayed in a first window, and a secondary set of said indices comprising a list of subject names is displayed in a second window, in response to a user selecting one of the category names. Finally, in response to a user selecting one of the subject names in the second window, the text in the subject name file corresponding to the subject name selected by the user is displayed in a third window.

System for automatic generation of arbitrarily indexed hyperlinked text

A system and method for increasing Operating System (OS) idle loop performance in a simulator environment. Upon encountering an OS idle loop condition on a processor, OS program flow is skipped ahead by an amount of time, thereby conserving the host machine's resources that would otherwise have been spent in supporting the OS idle loop execution. If another processor initiates an inter-processor message directed to a processor whose OS program flow has been skipped forward, that processor is capable of skipping backward in time, if necessary, to service the inter-processor message.

System and method for increasing OS idle loop performance in a simulator

A system and method for protecting a defined range of hardware addresses or a defined set of processor instructions from being accessed or executed by unauthorized software modules. Abstraction layer code is given a range of software addresses that are permitted to access the protected addresses or execute the instructions. Authorized accesses must utilize service routines provided by the abstraction layer code. When an attempted access to a protected hardware address is detected, it is determined whether the access is from the abstraction layer code. If so, the access is permitted. If not, the access is prohibited, and an error message is generated. A basic set of authorized processor instructions and an extended set of processor instructions may be defined for a reference platform. Execution of processor instructions in the extended set is limited to authorized abstraction layers. Otherwise, the attempted execution is prohibited, and an error message is generated.

System and method of limiting access to protected hardware addresses and processor instructions

A system and method for managing utilization in a stack. A stack base and a stack pointer are initialized for the stack. Upon fetching a program instruction to be executed in a computing environment, a determination is made if the program instruction involves accessing a location within a valid stack range that is defined by a high water mark operable to identify the stack pointer's farthest location from the stack base. The farthest location is indicative of how far the stack has grown at any time during the program's execution. A warning may be provided upon determining that the location to be accessed is not within the valid stack range.

Stack utilization management system and method for a single-stack arrangement

A system and method for setting and executing breakpoints utilized for debugging program code. A user interface (UI) stores breakpoint addresses in a breakpoint table within a central processing unit (CPU). Multiple breakpoint addresses may be stored in the table as a range of addresses in a single entry. A flag indicates whether each stored address or address range is a physical or virtual address. When executing the program code on the CPU, an instruction core requests from an instruction cache, an instruction associated with a particular address. The cache first determines from the breakpoint table within the CPU whether there is a breakpoint associated with the particular address. If so, the cache returns control to the UI. Otherwise, the cache goes out to a coherency controller to fetch the instruction from memory.

System and method for setting and executing breakpoints

A system and method for synchronizing processors simulated in an architectural simulator for a multiprocessor environment. A synchronous breakpoint is set at a predetermined address location and a code portion targeted for execution on the target multiprocessor environment is launched on the simulator from a fixed location. Upon automatically stepping through a list of processors initialized in the simulator until each of the processors reaches the synchronous breakpoint, run control is returned to the user only after all processors have achieved a synchronous state. Debug operations may ensue thereafter by utilizing a debugger integrated with the architectural simulator.

Synchronous breakpoint system and method

Simulated computer hardware is differentiated from physical computer hardware for user code by detecting a sequence of instructions which produce no effect on physical computer hardware but which set a flag on simulated computer hardware. User code may thus issue the sequence of instructions, then check the flag to determine whether it is executing on simulated hardware or physical hardware.

Method to distinguish between physical hardware and simulated hardware

A system and method for managing utilization in a unidirectional stack. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. The unidirectional stack is initialized via the API with respect to a fixed stack marker boundary, a stack base and a stack pointer. A high water mark is maintained for tracking the stack pointer's farthest location from the stack base during the execution of a program. When a program instruction is operable to access a stack location, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify the stack pointer, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

A system and method for managing stack utilization in a two-stack arrangement wherein the stacks are operable to grow towards each other. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. Each of two stacks is initialized via the API with a stack base, a growth direction indicator and a stack pointer. High water marks are maintained for tracking each stack pointer's farthest location from the respective stack base during the execution of a program. When a program instruction is operable to access a location in either of the stacks, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify either of the stack pointers, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

Growing community of inventors

Allen, TX, United States of America

Joe Bolding