Advanced Micro Devices Corporation

Globalfoundries Inc.

Joe Bloomquist

Manfred Horstmann

Peter Javorka

Jan Hoentschel

Andy C Wei

Christoph Schwan

Sven Beyer

Thorsten E Kammler

Frank Wirbeleit

Karla Romero

Markus Forsberg

Kai Frohberg

Gert Burbach

By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Semiconductor device comprising isolation trenches inducing different types of strain

By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

SOI transistor having a reduced body potential and a method of forming the same

By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions

A method of forming a field effect transistor comprises providing a substrate comprising, at least on a surface thereof, a first semiconductor material. A recess is formed in the substrate. The recess is filled with a second semiconductor material. The second semiconductor material has a different lattice constant than the first semiconductor material. A gate electrode is formed over the recess filled with the second semiconductor material.

Field effect transistor comprising a stressed channel region and method of forming the same

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

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Dresden, Germany

Joe Bloomquist