Marvellworld Trade Ltd.

Marvell International Limited

Jody Greenberg

Sehat Sutardja

Fernando De Bernardinis

Carlo Tinella

A calibration circuit for calibrating harmonics in a mixer. The calibration circuit includes an RF signal path configured to receive an RF signal corresponding to an output of the mixer, selectively receive a test signal injected into the RF signal path, and provide feedback to the mixer according to the RF signal and/or the test signal. The test signal corresponds to a selected harmonic of the harmonics in the mixer. A measurement circuit is configured to detect, in the output of the mixer, the test signal injected into the RF signal path. A calibration module is configured to receive a feedback signal indicative of the test signal detected in the output of the mixer and, based on the feedback signal indicative of the test signal detected in the output of the mixer, adjust a duty cycle associated with the mixer to calibrate the selected harmonic.

Calibration circuit and methods for calibrating harmonics in a mixer

A system includes a radio frequency (RF) signal path configured to receive an input signal that includes at least one of a test signal and an RF signal. A local oscillator (LO) signal path is configured to supply a LO signal. A mixer includes a first input in communication with the RF signal path and a second input in communication with the LO signal path. A calibration control module is configured to receive an output of the mixer in response to the test signal and to adjust an effective duty cycle of the LO signal in the LO signal path based on the output of the mixer.

Systems and methods for calibrating harmonic rejection in switching mixers

An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A variable capacitance circuit is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.

Variable capacitance with delay lock loop

A digital circuit configured to spread a clock train spectrum includes a clock configured to generate the clock train, and a variable divider configured to divide the frequency of the clock train by a temporally-varying-divider value to modulate the clock train and generate a dithered clock train. The circuit further includes a first accumulator configured to accumulate the dithered clock train to generate a frequency modulation waveform, and a second accumulator configured accumulate the frequency modulated waveform to generate a phase modulation signal. The circuit further includes a phase-value calculator configured to calculate the temporally-varying divider value based on the phase modulation signal; and a closed-loop control circuit configured to track and filter the modulation of the dithered clock train to generate a second clock train that is the spread spectrum of the first mentioned clock train.

All digital implementation of clock spectrum spreading (dither) for low power/die area

Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing.

Low-noise fine-frequency tuning

The disclosed device can contain a pair of switchable capacitors, one of which has the larger capacitance of the pair. Each of the switchable capacitors can include a capacitor in series with a switch. Both switchable capacitors can be connected in a parallel circuit that has a tunable capacitance. The ratio of the capacitances of the pair can approximately equal a ratio of mutually prime integers. In a particular case, the ratio of capacitances can approximately equal a ratio of two consecutive integers. The capacitance ratio can be called a weight or weight ratio. A switch controller can drive the pair of switchable capacitors with a pair of (M+1)-ary pulse width modulated signals, each of which has the same modulation period.

Digitally tunable capacitor

An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.

An integrated circuit includes a heating circuit configured to heat the integrated circuit under the control of a controller. A transfer function with adjustable pole, zero and overall gain is implemented in the controller such that a temperature response of the integrated circuit can be changed by adjusting one or more of the adjustable pole, zero and overall gain.

On-die heating circuit and control loop for rapid heating of the die

Circuits, methods, and apparatus that provide low-noise, high-stability crystal oscillators having controlled-amplitude differential output signals and DC level control. A crystal oscillator circuit has two feedback loops, one for setting the DC level of its signals, the other for adjusting the amplitude of those signals. The DC level feedback loop can set the DC component of the oscillator signals to a voltage midway between two supply voltages. The amplitude control loop sets the amplitude of the output of the crystal oscillator signal to be within a range. The amplitude can be set to provide a maximum swing without clipping the supply voltages in order to provide high-stability and minimal jitter. The amplitude control circuit can also be digital for improved noise performance. The time constants of these two loops can be separated such that instabilities are avoided.

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Sunnyvale, CA, United States of America

Jody Greenberg