International Business Machines Corporation

Globalfoundries Inc.

Jody B Joyner

Ravi Kumar Arimilli

Jerry Don Lewis

Guy L Guthrie

John Steven Dodson

Benjiman L Goodman

James Stephen Fields, Jr

Jeffrey A Stuecheli

Vicente Enrique Chung

Lakshminarayana Baba Arimilli

Charles David Wait

Bernard Charles Drerup

Jon K Kriegel

Sanjeev Ghai

Stephen J Powell

William John Starke

Jake Truelove

Bartholomew Blaner

Ronald Nick Kalla

Robert Dov Herzl

David A Campbell

Jay Gerald Heaslip

Michael Steven Siegel

Eric Eugene Retter

Bradley Nelson

Miles Robert Dooley

Aaron Christoph Sawdey

Benjamin Herrenschmidt

Glenn Owen Kincaid

Frederick Jacob Ziegler

Claude Basso

Colin Beaton Verrilli

Christoph Raisch

Hanhong Xue

William Elton Burky

Piyush Chaudhary

Paul Frank Lecocq

George W Rohrbaugh, Iii

Jan-Bernd Themann

Ronald Xavier Arroyo

David A Larson Stanton

A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.

Unified translation miss queue for multiple address translation modes

A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

Sleeping and waking-up address translation that conflicts with translation level of active page table walks

A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.

Power optimized prefetching in set-associative translation lookaside buffer structure

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

Promotion of ERAT cache entries

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.

Speculative checkin of ERAT cache entries

An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.

Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency

Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.

Reducing translation latency within a memory management unit using external caching structures

A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests are indicated for an accelerator unit (AU). In response to detecting that the invalidation requests are indicated, the MMU issues a raise barrier request for the AU. In response to detecting a raise barrier response from the AU to the raise barrier request the MMU issues the invalidation requests to the AU. In response to detecting an address translation invalidation response from the AU to each of the invalidation requests, the MMU issues a lower barrier request to the AU. In response to detecting a lower barrier response from the AU to the lower barrier request, the MMU resumes handling address translation check-in and check-out requests received from the AU.

Maintaining consistency between address translations in a data processing system

Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.

Ensuring forward progress for nested translations in a memory management unit

A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data processing system based on a memory access request received from a processor core. The memory controller receives an indication of an upcoming high latency event affecting access to the system memory. In response to the indication, the memory controller temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming high latency event.

Modification of prefetch depth based on high latency event

A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold

A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.

Techniques for cache injection in a processor system based on a shared state

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Austin, TX, United States of America

Jody B Joyner