Advanced Micro Devices Corporation

Other

Jody A McCoy

William Alexander Hughes

Michael L Choate

James F Headley

Leo J Klaes, Jr

Charles T Bloomer

A system for capturing the data necessary for synthesizing an instruction stream for a microprocessor. An embodiment uses a microprocessor that is adapted to write its branch trace data to the main memory. This branch trace data includes whether the microprocessor took each conditional jump encountered during the execution of a program as well as the target location of each indirect jump. The preferred embodiment further includes a logic analyzer coupled to the primary expansion bus of the target computer system. The logic analyzer captures input/output reads and writes as well as DMA transactions to the main memory. Finally, a synthesis control card controls starting a data capture as well as facilitating the transfer of information from buffers in the main memory to the control computer system. Using this information, a user may reconstruct the instruction steam as actually executed during a particular run of a program which may aide the user in performance analysis and design improvements for microprocessors.

Synthesizing the instruction stream executed by a microprocessor from its branch trace data

An apparatus is disclosed for capturing and transferring internal system activity of a computer under test. In one embodiment, the apparatus includes a bus interface, a memory, an external interface, and circuitry coupling the three together. The bus interface connects to an internal system bus of the system under test. The memory is for storing information indicative of internal system activity. The external interface couples to an external, monitoring system. The circuitry partitions the memory into at least two banks, each having multiple buffers. One of the multiple buffers in each bank is a trace buffer that receives instruction trace information from the processor of the system under test. The multiple buffers may further include a system memory image buffer, a processor data buffer, and a bus activity buffer. When any one of the buffers in a given bank of the memory becomes full, a bank switch occurs. Immediately prior to the bank switch, the contents of system memory are copied to the system memory image buffer, and the internal settings of the processor are similarly copied to the processor data buffer. Advantageously, if any errors are detected at this time, the previous memory bank still contains a pre-error snapshot of the processor contents and memory contents. Furthermore, the previous memory bank has an extensive record of pre-error bus activity and trace history. The external interface provides a means for transporting the memory bank contents to an external system continually, or alternately, whenever the memory bank contents are desired (e.g. when a fault is detected).

Apparatus and method for capturing and transferring internal system activity

A microprocessor is provided with an output pad logic circuit for each of its output lines. Each output pad logic circuit advantageously includes first and second latch circuits each configured to store output information at the same time. When the processor detects that a snoop write-back is pending, the second latch, referred to as a restore latch, preserves the information contained therein. During the snoop write-back operation, only the first latch stores the snoop write-back information and conveys the information to the output pins. When the snoop write-back operation is complete, an output enable signal is provided to the second latch to cause its stored information to be conveyed to the output pins upon the beginning of the next bus cycle. Subsequently, the second latch resumes capturing information along with the first latch. The output pad logic circuits within the microprocessor advantageously allow pipelined operations within the microprocessor and avoid the requirement of additional clock cycles to reload the output latch following a snoop write-back operation.

Microprocessor employing a technique for restoration of an aborted cycle

The present invention includes a method and apparatus for performing intrusive testing upon a microprocessor to ensure the absence of errors or defects in performance-enhancing features and related control circuitry which affect the results of software instructions being executed by the microprocessor. In the intrusive testing method, an intrusive testing unit capable of generating logic signals is coupled between a computer system motherboard and a microprocessor. The microprocessor is then caused to execute a test software program. As the microprocessor executes the test software program, the intrusive testing unit generates logic signals (alternate control signals) at regular intervals. Control signals generated by system hardware on the motherboard in response to program execution are logically combined with alternate control signals generated by the intrusive testing unit. Resulting output control signals are applied to the control signal pins of the microprocessor. The intrusive testing unit thus ensures a large number of control signals are applied to the microprocessor in a relatively short period of time. The computer system is monitored to determine proper execution of the test software program.

Method and apparatus for intrusive testing of the performance-enhancing

The present invention provides an alternative circuit for microwave oscillators. The invention consists of an amplifier, signal divider, filter(s), and optional limiter. The feedback path is external to the amplifier, allowing direct access and control of the loop phase and loop gain. Control of the loop gain can be used for applications such as amplitude modulation of the oscillator's output or control of the oscillator's output power. Control of the loop phase can be used to frequency modulate the oscillator or to create a voltage-controlled oscillator. Dynamic control of the loop gain with a limiter enables one to maintain linear operation throughout the oscillator. Linear operation is often desirable to eliminate the 1/f noise contributions at the frequency of operation and to enable the use of small signal s-parameters in the design and analysis.

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Austin, TX, United States of America

Jody A McCoy