Lattice Semiconductor Corporation

Jock F Tomlinson

Om P Agrawal

Ju Shen

Jinghui Zhu

David Clark Wilkinson

Ji Zhao

Kuang Chi

Douglas C Morse

James J Bennett

Michael W Lottridge

Guy A Townsend

In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.

SERDES with programmable I/O architecture

In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.

A programmable power management integrated circuit includes analog input monitors that receive analog input signals that correspond to voltage, current, or temperature measurements. The analog input monitors apply programmable thresholds to the measurements and output the results to a programmable logic device, which may generate various status and/or control signals to the system being monitored. The programmable logic device controls FET drivers that can switch on and off power to the monitored system. The programmable power management integrated circuit may also comprise an internal oscillator, a serial interface, an in-system programmable interface, a joint test action group interface, a memory that stores identification information, and a register for capturing system information during power-down.

Programmable power management system and method

A method for programming an in-system programmable logic device (IsPLD), using an automatic tester, includes the steps of: (i) expressing a fuse map for an IsPLD in the form of one or more test vectors to be applied in an automatic tester; (ii) including in a system board unprogrammed the IsPLD; (ii) mounting the system board on an automatic tester in a configuration for system testing; (iii) receiving into the automatic tester the test vectors; and (iv) and apply the test vectors to program the IsPLD. The system board with the IsPLD so programmed can proceed immediately to final test. In addition, a method is provided to translate a JEDEC file to a bit stream file, thereby achieving a eight-fold saving in storage requirement.

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Beaverton, OR, United States of America

Jock F Tomlinson