International Business Machines Corporation

Globalfoundries Inc.

Jochen Supper

Andreas Huber

Hubert Harrer

Bruno Michel

Thomas J Brunschwiler

Harry S Barowski

Stephan Paredes

Tim Niggemeier

Roland Frech

Erich Klink

Jonas R Weiss

Roger F Dangel

Norbert M Meier

Martin Eckert

Otto Andreas Torreiter

Thomas-Michael Winkel

Anand Haridass

Thomas Strach

Claudio Siviero

Martin Bernhard Schmidt

Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.

Mitigating power noise using a current supply

A method for determining power consumption of a power domain within an integrated circuit is presented. In a first step, a local power supply impedance profile (Z(f)) of this power domain is determined. Subsequently, a local time-resolved power supply voltage (U(t)) is measured while a well-defined periodic activity is executed in power domain. A set of time-domain measured voltage data (U(t)) is thus accumulated and transformed into the frequency domain to yield a voltage spectrum (U(f)). A current spectrum I(t) is calculated from this voltage profile (U(f)) by using the power supply impedance profile Z(f) of this power domain as I(t)=F{U(f)/Z(f)}. Finally, a time-resolved power consumption spectrum P(t) is determined from measured voltage spectrum U(t)) and calculated current spectrum (I(t)). This power consumption (P(t)) may be compared with a reference (P(t)) to verify whether power consumption within power domain matches expectations.

Measuring power consumption in an integrated circuit

A computer program product or hardware description language ('HDL') design structure in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

Transferring heat through an optical layer of integrated circuitry

Network power fault detection. At least one first network device is instructed to temporarily disconnect from a power supply path of a network, and at least one characteristic of the power supply path of the network is measured at a second network device connected to the network while the at least one first network device is temporarily disconnected from the network.

Network power fault detection

An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink.

A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

Integrated circuit package connected to an optical data transmission medium using a coolant

An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L-L) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l-l), wherein n&#x2267;1 and N&#x2267;2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.

Integrated circuit package connected to a data transmission medium

A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z(f).

Method and system for performing self-tests in an electronic system

A method for determining a power supply impedance profile (|Z(f)|) at a predetermined load location within an electronic system. A repetitive activity (such as a modulated clock tree signal) is applied in the load location, and the local power supply voltage (U(t)) caused by this repetitive activity is measured. Rather than measuring the corresponding current consumption (I(t)) caused by the repetitive activity, the current consumption is calculated analytically. The local power supply impedance profile (|Z(f)|) is calculated as the ratio of the frequency-domain voltage and current consumption magnitudes (|U(f)|, |I(f)|) of the measured power supply voltage (U(t)) and the calculated current consumption (I(t)).

Method and system for impedance measurement in an integrated Circuit

A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Optimized semiconductor packaging in a three-dimensional stack

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Thermal power plane for integrated circuits

A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Heat sink integrated power delivery and distribution for integrated circuits

A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.

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Herrenberg, Germany

Jochen Supper