Adv Antest Corporation

Agilent Technologies, Inc.

Verigy (singapore) Pte. Ltd.

Advantest (singapore) Pte Ltd

Hewlett-packard Company

Verigg Ipco

Verigy Pte. Ltd.

Jochen Rivoir

Ajay Khoche

Markus Rottacker

Andreas Hantsch

Linda Argon Kamas

Joseph Michael Gorin

Erik H Volkerink

George Stennis Moore

Takanori Komuro

Matthew Johnson

Bernd Laquai

Klaus-Dieter Hilliges

Peter J Cain

Markus Seuring

Holger Engelhard

Moray Denham Rumney

Marc Moessinger

Klaus-Peter Behrens

Marco Pausini

David H Molinari

David H Armstrong

John Francis McLaughlin

Dieter Ohnesorge

Christoph Zender

Alfred Rosenkraenzer

Christian Sebeke

Robert Locascio

Tilmann Wendel

Hugh S C Wallace

Herbert Tiedemann

Systems and methods for performing device testing using automatic test equipment that can advantageously utilize relatively large numbers of test scenarios and activities including multiple test steps and resources and that prevents test parameters from conflicting or colliding to improve test performance and accuracy are disclosed herein. The test activities of a given test scenario can be configured to be executed concurrently. The test activities can be associated with one or more test parameters characterized by respective test parameter values and/or are associated with one or more constraints.

Systems and methods for device testing to avoid resource conflicts for a large number of test scenarios

A tester for testing a device under test is shown, having a test unit configured for performing a test of the device under test using multiple test cases, each test case having variable values of a set of predetermined variables, the test units configured to derive an output value for each test case indicating whether the device under test validly operates at a current test case or whether the device under test provides an error at the current test case; and an evaluation unit configured for evaluating the multiple test cases based on a plurality of subsets of the predetermined input variables with respect to the output value, the evaluation unit configured for providing a number of plots of the evaluation of the multiple test cases where each plot indicates the impact of one subset of the plurality of subsets of the predetermined input variables to the output value in dependence on respective relevance scores or associated with the respective relevance scores.

Tester and method for testing a device under test using relevance scores

An automated test equipment for testing devices under test is configured to combine different output signals from multiple pins of a single device under test or from pins of a plurality of devices under test to obtain a combined signal; and to extract individual signals or properties of the individual signals from the combined signal.

Automated test equipment for combined signals

A test apparatus for performing a test on a device under test includes a data storage unit being configured to store sets of input data applied to the device under test during the test and to store the respective output data of the device under test, the output data being obtained from the device under test as a response to the input data including values of setting variables related to settings of the device under test and values of input variables including further information, each set of input data representing one test case; and a data processor configured to process the data stored in the data storage unit such that a best combination of setting variables of the device under test is determined for one or more combinations of the input variables to obtain an optimized setting of the device under test for the one or more combinations of the input variables.

Test apparatus for performing a test on a device under test and data set filter for filtering a data set to obtain a best setting of a device under test

An apparatus for determining a single decision function is configured to obtain measurements from a plurality of devices under test corresponding to stimulating signals applied to the plurality of devices under test. The stimulating signals correspond to a set of tests performed on the plurality of devices under test. The apparatus may further determine a subset of tests from the set of tests, such that the subset of tests is relevant for indicating whether the plurality of devices under test pass the set of tests. The apparatus may also determine the single decision function applicable to measurements from an additional device under test tested using the subset of tests, such that the single decision function is adapted to predict a test result for the set of tests on the basis of the subset of tests.

Tester and method for testing a device under test and tester and method for determining a single decision function

A test apparatus for characterizing a device under test includes a test case generator, a test unit, a data storage unit, and a data analysis unit. The test case generator is configured to randomly generate a plurality of test cases, which include values of one or more input variables of a set of input variables. The test unit is configured to perform the plurality of test cases on the device under test. The data storage unit may store sets of test data, which are associated to the test cases and include values of input variables of a respective test case and corresponding values of output variables of the device under test related to the respective test case. The data analysis unit may further analyze the test data and is further configured to determine dependencies within a subset of variables of the test data to characterize the device under test.

Test apparatus and method for characterizing a device under test

A test apparatus for testing a device under test is configured to receive a response signal from the device under test and to apply one or more correction functions to the received response signal to at least partially correct an imperfection of the DUT. The test apparatus is configured to thereby obtain a corrected response signal of the device under test and to evaluate the corrected response signal to judge the device under test.

Test apparatus and method for testing a device under test

An apparatus for wireless testing, wherein the apparatus includes a test interface, a test generator, a test module, and an analysis module. The test interface is coupled to an electronic device and is configured to transmit data to the electronic device and to receive data from the electronic device. The test generator drives the electronic device through the test interface to vary the beam direction. The test module determines a plurality of transmit values of a transmit parameter based on the test signal wirelessly received from the electronic device using at least one static antenna for receiving the test signal. Each transmit value of the transmit parameter is associated with a different beam direction. The analysis module provides an assessment of the plurality of transmit paths of the electronic device based on the plurality of transmit values.

Apparatus and method for wireless testing of a plurality of transmit paths and a plurality of receive paths of an electronic device

A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination.

Techniques for determining a fault probability of a location on a chip

A bit sequence generator for generating a bit sequence defined by a generating function and an initial state of the generating function comprising a plurality of state machines and a multiplexer. Each state machine of the plurality of state machines generates a time-interleaved bit sequence, wherein a state machine generates a bit of the time-interleaved bit sequence for a current time step based on at least one bit generated by the state machine for a preceding time step, the generating function of the bit sequence to be generated, and the initial state of the generating function and independent from a time-interleaved bit sequence generated by another state machine of the plurality of state machines. Further, a multiplexer selects successively one bit from each generated time-interleaved bit sequence in a repetitive manner to obtain the bit sequence defined by the generating function and the initial state of the generating function.

Bit sequence generator and apparatus for calculating a sub-rate transition matrix and a sub-rate initial state for a state machine of a plurality of state machines

A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.

Device under test data processing techniques

An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges.

Apparatus for determining a number of successive equal bits preceding an edge within a bit stream and apparatus for reconstructing a repetitive bit sequence

Systems and methods for measuring a phase noise of a test signal. A test system includes a recursive delayer, a combiner and a phase noise determinator. The recursive delayer is configured to provide a recursively delayed signal on the basis of the test signal. The combiner is configured to combine a first signal with a second signal to provide a combiner output signal. The first signal is generated based on the test signal and the second signal is generated based on the recursively delayed signal. The phase noise determinator is used to determine phase noise information based on the combiner output signal.

Apparatus comprising a recursive delayer and method for measuring a phase noise

The present invention relates to a method for adjusting transitions in a bit stream of a signal to be evaluated by comparison with a predetermined expected bit stream, comprising the steps of receiving said bit stream signal by a transition adjustment filter, providing a transition frame signal to said transition adjustment filter, said transition frame signal providing information for eliminating non-deterministic clock latencies within said bit stream of said received signal, and adjusting said bit stream of said received signal according to said transition frame signal resulting in an adjusted bit stream being in alignment to said expected bit stream.

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Magstadt, Germany

Jochen Rivoir