Itt Industries, Inc.

Jochen Reimers

Mathew Neal

Between the source of operating voltage (U) and the zero point of the circuit there are provided four series arrangements (s1 . . . s4) of the controlled current paths of each time three insulated-gate field-effect transistors of the same conductivity type, of which the upper transistors (o1 . . . o4) as connected to the source of operating voltage, and the center transistors (m1 . . . m4) are of the depletion type and of identical geometry, while the lower transistors (u1 . . . u4) as connected to the zero point of the circuit, are of the enhancement type and likewise of identical geometry. The center transistors (m1, m3, m4) are connected as a resistors while the gate of the center transistor (m2) is connected to the point connecting the upper and the center transistor (o4, m4). The first input (e1) is connected to the gates of the upper transistors (o1, o3) and the second input (e2) to the gates of the upper transistors (o2, o4). The output of the inverter as formed by the series arrangements (s1 . . . s4) is the point connecting the respective lower and center transistors. The gates of the lower transistors (u2 . . . u4) are each connected to the output of the directly preceding inverter, while the gate of the lower transistor (u1) is connected to the output of its inverter, with the output of the fourth inverter being the output (a) of the comparator circuit.

Growing community of inventors

Gundelfingen, Germany

Jochen Reimers