Infineon Technologies Ag

Jochen M&uuml;ller

Justus Kuhn

Gunnar H Krause

Peter P&ouml;chm&uuml;ller

Michael Schittenhelm

Jens L&uuml;pke

Matthias Lehr

J&uuml;rgen Lindolf

Wolfgang Ernst

Harry Hedler

Dominique Savignac

Helmut Fischer

Dietrich Widmann

Barbara Vasquez

Axel Brintzinger

Ulrich Frey

Stefan Dankowski

Kamel Ayadi

Rene Tews

Michael H&uuml;bner

J&uuml;rgen Weidenh&ouml;fer

Peter Pochm&uuml;ller

Armin Wieder

Dieter Kantz

A test configuration for the functional testing of a semiconductor chip is described. The semiconductor chip, which can be subjected to a functional test for the purpose of checking the functionality of the semiconductor chip, is disposed on a support material. The semiconductor chip contains a self-test unit for generating test information and for carrying out the functional test. An energy source serves for providing an electrical energy supply from energy that is fed in contactlessly. The energy source is disposed on the support material and is connected to the semiconductor chip for the purpose of providing an energy supply on the semiconductor chip. The test configuration makes it possible to carry out a contactless functional test and to reduce the test costs by virtue of high parallelism during the functional test of a plurality of semiconductor chips.

Test configuration for the functional testing of a semiconductor chip

A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Test configuration and test method for testing a plurality of integrated circuits in parallel

A lowermost layer of control chips carries on it layers of memory chips. The memory chips are contacted via looped-through contacts that reach from one side of the other side of the memory chips and they are driven by the control chips that contain the test circuit for the memory chips.

Semiconductor chip, memory module and method for testing the semiconductor chip

The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

System for testing fast integrated digital circuits, in particular semiconductor memory modules

An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.

Integrated semiconductor memory device

The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

System for testing fast synchronous semiconductor circuits

An integrated semiconductor circuit, in particular a semiconductor memory configuration, which can be operated in various operating modes and which has an apparatus for switching between these operating modes is described. The semiconductor circuit has a switching apparatus with at least one fuse unit, which can be blown and programmed from the exterior.

Integrated semiconductor circuit, in particular a semiconductor memory configuration, and method for its operation

An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Field-effect-controlled transistor and method for fabricating the transistor

The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate ( ); providing a metallization region ( ) comprising a first metal in the circuit substrate ( ); providing a first insulation layer ( ) above the metallization region ( ); forming an opening ( ) in the insulating layer ( ) in order to uncover at least part of the surface of the metallization region ( ); depositing a functional layer ( &prime;) above the resulting structure; depositing a second insulating layer ( ) above the resulting structure, in such a manner that the opening ( ) is filled; polishing-back of the second insulating layer ( ) and of the functional layer ( &prime;) in order to uncover the surface of the first insulating layer ( ); forming a contact ( &prime;) in the second insulating layer ( ) inside the opening ( ) in order to make contact with the functional layer ( &prime;); and providing an interconnect ( ) for electrical connection of the contact ( &prime;).

Method for fabricating an integrated circuit, in particular an antifuse

A connection element in an integrated circuit having a layer structure disposed between two conductive structures. The layer structure is formed by an insulating layer, which can be destroyed by application of a predetermined voltage, and a silicon layer. The insulating layer adjoins a first conductive structure made of tungsten.

Connection element in an integrated circuit having a layer structure disposed between two conductive structures

The invention relates to a fusible link configuration in or on integrated circuits, in particular highly integrated memory chips, in which in each case one bank of fusible links (F , F , . . . ), together with an evaluation logic unit is configured beside and in association with a memory field segment. The evaluation logic unit is electrically connected to the fusible links (F , F , . . . ) and determines whether one or more of the fusible links (F , F , . . . ) is severed. One or more banks of the fusible links (F , F , . . . ) are divided up into smaller units while restricting the width(s) of the bank or banks. The units are grouped such that at least some of the fusible links (F , F , . . . ) are located beside one another transversely with respect to the width direction of the bank.

Growing community of inventors

München, Germany

Jochen Müller

Growing community of inventors

München, Germany

Jochen M&uuml;ller

Jochen Müller