Nordic Semiconductor Asa

Joar Rusten

Lasse Olsen

Anders Nore

Lars Sundell

Junaid Elahi

Arne Wanvik Venas

Ronan Barzic

Vegard Endresen

Per-Carsten Skoglund

Steffen Wiken

Arne W VENÅS

A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.

Inter-processor communication

An integrated-circuit device comprises first and second peripherals, connected to a processor via a bus system, a peripheral interconnect that is separate from the bus system, wake up logic, a configuration memory and a power controller. In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response. The first peripheral, second peripheral and the wake-up logic are in a first, second and third power domain respectively. The power controller provides power to the third power domain whenever the first or second power domain is powered up. The wake-up logic detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral.

Peripheral power domains

An electronic data processing device comprises: a processor (); a serial interface comprising a connection for incoming data () and a connection for outgoing data (); a hardware serial-interface controller () for controlling the serial interface; and a reception buffer () for receiving incoming data. The processor is arranged automatically to read data written to the reception buffer. The device is arranged so that the processor can indicate to the serial interface controller that it is unable to accept data. The controller is arranged to respond to incoming data by sending a rejection message from the outgoing serial connection and to prevent incoming data from being placed in the reception buffer.

Data processing

A microcontroller () comprises a processor (), a memory (), a bus () connecting the processor () and the memory () and a memory watch unit (), comprising one or more memory-watch event registers and one or more configuration registers. The memory watch unit () is arranged to monitor memory access instructions on the bus (), and can be configured, using the one or more configuration registers, to (i) detect a memory access instruction for a memory address in a configurable watch region of the memory (), and (ii) change the contents of one or more memory-watch event registers in response to such a detection.

Memory watch unit

A microcontroller () has a processor (), peripherals (), a programmable peripheral interconnect (PPI) (), an event-generating unit (EGU) (), and a memory (). The peripherals respond to task signals from the PPI. The EGU responds to a predetermined change to the contents of an event-generating register () by signalling an event to the PPI. Stored PPI mappings can map an EGU event to a task of one of the peripherals. Mappings from one EGU event to two or more peripheral tasks cause the PPI to respond to an event signal from the EGU by sending the respective task signals within a maximum time limit. Software in the memory comprises instructions to store such mappings in a mapping memory, and to make the predetermined change to the contents of the event-generating register. In another aspect, an interrupt-generating unit () is arranged to send an interrupt to the processor () in response to receiving a task signal from the PPI ().

Event generating unit

A microprocessor comprises a timer capable of resetting the device and a plurality of hardware registers () arranged logically so that a collective predetermined state of the registers () prevents the device from resetting. The device further comprises software () with a plurality of functions arranged to place said registers () in said predetermined state if each of said functions has executed properly.

Microprocessor device with reset timer

Peripherals () are connected to a processor () and a programmable peripheral interconnect () is connected to each peripheral. One of the peripherals () is configured to signal an event to the interconnect, and one of the peripherals () is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral () has a task register (), addressable by the processor (), and performs the task in response to a change in the contents of the register (). The interconnect () accesses a memory () in which a mapping is stored between an event of a first peripheral () and a task of a second peripheral (), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (). The mapping causes the interconnect () to provide a channel by sending a task signal to the second peripheral () in response to a signal of the event from the first peripheral ().

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Trondheim, Norway

Joar Rusten