Stmicroelectronics (crolles 2) Sas

Koninklijke Philips Corporation N.V.

Other

Nxp B.v.

Stmicroelectronics S.a.

Stmicroelectronics (corlles 2) Sas

Joaquin Torres

Laurent-Georges Gosset

Vincent Arnal

Sonarith Chhun

Laurent Gosset

Nicolas Jourdan

Philippe Coronel

Alexis Farcy

Michel Marty

Pascal Ancey

Srdjan Kordic

Francois Leverd

Pascale Motte

Brigitte Descouts

Maryline Thomas

Wim Besling

Laurant Georges Gosset

The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.

Copper diffusion barrier

The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing () an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing () a dielectric liner on the interconnect surface; removing () at least part of the dielectric liner on the interconnect surface; successively repeating () the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming () at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.

Integration of self-aligned trenches in-between metal lines

A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.

MIM capacitor with enhanced capacitance

An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.

Control of carbon nanostructure growth in an interconnect structure

A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:&#x2014;providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;&#x2014;depositing a metal layer on the exposed surface of conductive element;&#x2014;inducing diffusion of metal from the metal layer into a top section of the conductive element;&#x2014;removing the remaining metal layer;&#x2014;letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

Fabrication of a diffusion barrier cap on copper containing conductive elements

A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.

Method for forming metal interconnects in a dielectric material

Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.

Controlling lateral distribution of air gaps in interconnects

The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combination provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate-circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device.

CuSiN/SiN diffusion barrier for copper in integrated-circuit devices

The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with different crystal orientations

A capacitor formed in an insulating porous material.

MIM capacitor

An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance of the semiconductor interconnects.

Integration control and reliability enhancement of interconnect air cavities

A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.

Process for fabricating an integrated electronic circuit that incorporates air gaps

The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding fabrication process

Growing community of inventors

Saint Martin le Vinoux, France

Joaquin Torres