Netapp, Inc.

Cacheiq, Inc.

Other

Cisco Technology, Inc.

Tippingpoint Technologies, Inc.

Joaquin J Aviles

Gregory A Dahl

Mark U Cree

Gerald Stellenberg

Craig D Botkin

Ronald E Battles

A method, system and program are disclosed for accelerating data storage in a cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files using dynamically adjustable cache policies which populate the storage cache using behavioral adaptive policies that are based on analysis of clients-filers transaction patterns and network utilization, thereby improving access time to the data stored on the disk-based NAS filer (group) for predetermined applications.

System and method for populating a cache using behavioral adaptive policies

A method, system and program are disclosed for accelerating data storage by providing non-disruptive storage caching using clustered cache appliances with packet inspection intelligence. A cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files using dynamically adjustable cache policies provides low-latency access and redundancy in responding to both read and write requests for cached files, thereby improving access time to the data stored on the disk-based NAS filer (group).

Clustered cache appliance system and methodology

A method, system and program are disclosed for accelerating data storage by providing non-disruptive storage caching using spliced cache appliances with packet inspection intelligence. A cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files using dynamically adjustable cache policies provides low-latency access and redundancy in responding to both read and write requests for cached files, thereby improving access time to the data stored on the disk-based NAS filer (group).

Non-disruptive storage caching using spliced cache appliances with packet inspection intelligence

A method, system and program are disclosed for accelerating data storage in a cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a cache memory by using a perfect hashing memory index technique to rapidly detect predetermined patterns in received packet payloads and retrieve matching patterns from memory by generating a data structure pointer and index offset to directly address the pattern in the datagram memory, thereby accelerating evaluation of the packet with the matching pattern by the host processor.

Method and apparatus for matching trigger pattern

A method, system and program are disclosed for accelerating data storage in a cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a cache memory by using a dual hash technique to rapidly store and/or retrieve connection state information for cached connections in a plurality of index tables that are indexed by hashing network protocol address information with a pair of irreducible CRC hash algorithms to obtain an index to the memory location of the connection state information.

Dual hash indexing system and methodology

A method, system and program are disclosed for accelerating data storage in a cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a multi-rank flash DIMM cache memory by pipelining multiple page write and page program operations to different flash memory ranks, thereby improving write speeds to the flash DIMM cache memory.

Flash DIMM in a standalone cache appliance system and methodology

A pattern matching engine supports high speed (up to at least 2.4. Gbits per second line rate speeds) parallel pattern matching operations in an unanchored fashion. The engine is preferably implemented as a hardware device. A shift register serially receives a string of data stream bytes which are partitioned into a plurality of multi-byte overlapping adjacent stream chunks. Library patterns of bytes to be searched for are similarly partitioned into multi-byte overlapping adjacent table chunks for storage in a look-up table. The plurality of multi-byte overlapping adjacent stream chunks are applied by the register in parallel to the look-up table, with a result being returned which is indicative of whether each stream chunk matches one of the look-up table stored table chunks. The results of the parallel look-up operation are then logically combined to make a match determination.

Method and apparatus for data packet pattern matching

A system and method provides for the conversion of disparate physical interfaces. The system and method includes one or more serial interfaces that interface with devices having disparate serial interfaces. One or more physical modules, associated with the serial interfaces, interface with one or more components having disparate physical interfaces but that do not support serial interfaces. The physical modules are able to interface with a variety of different components having different physical interfaces. A conversion module associated with the physical modules and the serial interfaces serializes or deserializes the data transmitted between the physical modules and the serial interfaces. A plurality of queues order the data transmissions between the components and the serial interfaces to prevent data bottlenecks. A backplane may be utilized as the facility for high speed communication allowing the components having disparate physical interfaces to interface with each other and the backplane.

System and method for disparate physical interface conversion

A system and method for coupling a local bus to a PCI bus are provided. The system comprises a local bus interface for receiving signals from a microprocessor through a local address/data bus and a local control bus. The system further comprises a bus translator coupled to the local bus interface. The bus translator determines if the microprocessor will access a target peripheral PCI device coupled to the local address/data bus. A PCI control bus interface is coupled to the bus translator and signals the target PCI peripheral device via a PCI control bus, such that the local address/data bus and the PCI control bus define a PCI bus.

Growing community of inventors

Austin, TX, United States of America

Joaquin J Aviles