Stmicroelectronics S.a.

Commissariat a L'energie Atomique

L'etat Francais

France Telecom/cnet

Etat Francais Centre National De La Recherche Scientifique

Joaquim Torres

Vincent Arnal

Jean Palleau

Alexis Farcy

Michel Haond

Philippe Gayet

Roland Madar

Andre Schiltz

Claude Bernard

Pascale Motte

Brigitte Descouts

Noureddine Bourhila

Jean-Francois Million-Brodaz

A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.

High-frequency line

A method for depositing a dielectric material on copper apparent on the surface of a structure, by placing the structure in a depositing chamber of CVD type (Chemical Vapor Deposition), adding to the chamber a first gas forming a precursor for the formation of the dielectric material and containing an element able to contaminate copper, adding to the chamber a second gas containing a chemical element intended, together with the element contained in the first gas and able to contaminate copper, to form said dielectric material, the second gas being able to react with the first gas to give the deposit of dielectric material, performing the deposit of dielectric material from the first gas and the second gas, characterized in that the method comprises a step for adding a third gas able to prevent the contamination of copper by said element contained in the first gas.

Method for depositing a silicon-containing dielectric material on copper

A method for forming a capacitor with metal armatures in metallization levels above an integrated circuit, including the steps of: depositing over the surface of an integrated circuit an insulating layer having a thickness ranging between 0.5 and 1.5 &mgr;m; digging into the insulating layer to form trenches, of which at least a portion in top view is parallel and separate from one trench to the other; depositing and leveling a metallic material to form conductive lines in the trenches; locally removing the insulating layer to remove it at least from all the intervals separating two conductive lines; conformally depositing a dielectric; and depositing and etching a second metallic material to at least completely fill the intervals between lines.

Manufacturing of capacitors with metal armatures

An inductance formed in an integrated circuit chip, formed of a plurality of parallel conductive lines, of optimized width, each conductive line being formed in the thickness of at least one insulating layer, these lines being interconnected by at least one perpendicular conductive segment.

High-frequency integrated inductive winding

One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

Method of forming insulated metal interconnections in integrated circuits

A lift-off process for removing a portion of a metal layer (4). The metal layer is formed on a dielectric polymer substrate with interposition of a corresponding portion of an intermediate layer (2). This process comprises the steps of selecting the material of the intermediate layer so that its interface with the metal has a low adhesivity; applying to the structure a mechanical stress causing detachment of the metal at the interface; and chemically removing the intermediate layer.

Mechanical lift-off process of a metal layer on a polymer

A process for forming tungsten or molybdenum silicide on silicon apparent regions (6) of a silicon wafer surface (1) also comprising oxidized regions (2) includes the steps consisting in uniformly coating the wafer with a tungsten or molybdenum layer (10) and annealing at a temperature ranging from 700.degree. C. to 1000.degree. C. The annealing step is carried out in presence of a low pressure gas forming a chemical composite with tungsten or molybdenum. The composite is then selectively etched.

Tungsten silicide self-aligned formation process

A selective deposition process of a refractory metal silicide onto the silicon apparent surfaces of a wafer partially coated with SiO.sub.2, comprising the following steps: flowing in a cold-wall airtight chamber comprising said wafer a gaseous silane composite at a partial pressure P.sub.Si.sbsb.x.sub.H.sbsb.y and an halogenide of said metal at a partial pressure P.sub.Me ; heating the wafer to a first temperature (T1) for a first duration (t1), P.sub.Si.sbsb.x.sub.H.sbsb.y and P.sub.Me being chosen so as to allow a metal silicide deposition to be formed on the wafer, the silicon being overstoichiometric; and, heating the wafer to a second temperature (T2) lower than the first one for a second duration (t2), T2 being chosen as a function of P.sub.Si.sbsb.x.sub.H.sbsb.y and P.sub.Me so as to allow a stoichiometric metal silicide deposition to be formed on the wafer.

Growing community of inventors

Saint Martin le Vinoux, France

Joaquim Torres