U.S. Philips Corporation

Hewlett-packard Company

Philips Electronics N.v.

Joao N Ramalho

Johannes O Voorman

Bradley K Davis

Eric B Desbonnets

Patrice Gamand

An automatic gain control circuit, for amplifying an input signal so that it has a specific correspondence with a reference value (V.sub.ref), includes an input terminal (2) for receiving the input signal, a variable gain amplifier (4) for amplifying the input signal in response to a gain control signal, a peak detector (14) for detecting peaks in the amplified input signal, the peak detector (14) having an attack time constant (T.sub.a) and a decay time constant (T.sub.d), and supplying a peak detector output signal (V.sub.p) representative of the amplitude of the peaks in the amplified input signal, a comparator (20) for comparing the peak detector output signal (V.sub.p) with the reference value (V.sub.ref) to form an error signal (e), and an integrator (30) for integrating the error signal (e) to form the gain control signal. The peak detector includes a controller for controlling the decay time constant in response to the error signal, the controller decreasing the decay time constant for increasing error signals, in a situation when the peak detector output signal (V.sub.p) is larger than the reference value (V.sub.ref). The relationship, T.sub.d =c.multidot.T.sub.a.sup.p, is maintained between the attack time constant T.sub.a and the decay time constant T.sub.d of the peak detector, where c is a positive constant and p is a constant larger than 1. p is preferably equal to 2 and c satisfies the relation 20.ltoreq.c.ltoreq.200.

Automatic gain control circuit for use in detecting servo pulses for

A write amplifier comprising four current mirrors which are turned on two at a time by two switchable floating current sources between the input terminals of the current mirrors in order to produce a write current of alternating polarity through the write head. The parasitic capacitances across the write head and/or the parasitic capacitances of the write amplifier at the write terminals are compensated by means of feed-forward capacitors. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit.

Arrangement comprising a magnetic write head, and write amplifier with

An arrangement for reading out an information signal from a magnetic record carrier. The arrangement includes a read head having a magneto-resistive (MR) element (R.sub.m1) with a first terminal (3) connected to a first point (13) of constant potential, and a second terminal (4); a bias-current generator (2) having an output (5) for supplying a bias-current to the MR element; and an amplifier circuit (1) having a first terminal (6) coupled to the output (5) of the bias-current generator (2), and a second terminal (7) coupled to the second terminal (4) of the magneto-resistive element (R.sub.m1) so as to form a series arrangement of the bias-current generator, the amplifier circuit and the magneto-resistive element. At an output terminal (8), the information signal is available. The amplifier circuit (1) includes a MOS transistor T.sub.1 coupled between the output terminal (8) and the second terminal (7), and a feedback circuit, including a resistor (R.sub.1) and a capacitor (C.sub.1), having a low cut-off frequency (R.sub.1,C.sub.1) which provides a bias voltage to the gate of the MOS transistor (T.sub.1) and forces the bias-current of the bias-current generator (2) to flow through the MR element. Fast settling of the arrangement is possible by short-circuiting, via a switch (S.sub.1), the resistor (R.sub.1), a high charge current for capacitor C.sub.1 being supplied by a buffer amplifier (310). The buffer amplifier (310), the resistor R.sub.1 and the switch S.sub.1 provide fast settling without generating undesired off-set.

Arrangement for reading information from a track on a record carrier

A preamplifier circuit for a computer data storage system disk drive read/write head (or HSA) includes multiple test modes to enable electrical testing of the preamplifier, the read/write heads, and associated circuitry without physically probing the components or circuitry. Communication between the preamplifier and a host controller provides for test mode selection and test mode enablement within the preamplifier. Testing occurs using only the normal interface connector to the head disk assembly (HDA) in which the preamplifier and HSA are embodied. Properties such as electrical resistance, ESD, preamplifier bond wire connection integrity, head bond wire and solder joint integrity, and connections from the head slider to the preamplifier leads are all tested. Testing occurs without probing to provide efficient, reliable, and cost effective manufacturing and testing benefits of the read/write heads, flex assembly, HSA, and HDA.

Circuit and method for testing a disk drive head assembly without probing

A differential amplifier with common-mode rejection for low supply voltages has a first and a second differential pair without transistors in the tails of the differential pairs and with proportional common-mode currents flowing through the first and the second differential pair. The differential amplifier includes a current mirror which feeds the common-mode current of the second differential pair (3, 4) back to the output terminals of the first differential pair for the rejection of common-mode currents at the output terminals. The voltage at the output terminals of the current mirror has a d.c. level which can be established by means of a first reference voltage source independently of the common-mode voltage at the input terminals of the differential amplifier.

Differential amplifier with common-mode rejection for low supply voltages

An arrangement for reading out an information signal from a magnetic record carrier. The arrangement includes a read head having a magneto-resistive element with a first terminal connected to a first point of constant potential, and a second terminal; a bias-current generator having an output for supplying a bias-current to the MR element and an amplifier circuit having a first terminal coupled to the output of the bias-current generator, and a second terminal coupled to the second terminal of the MR so as to form a series arrangement of the bias-current generator, the amplifier circuit and the MR element. At an output terminal of the amplifier circuit, the information signal is available. The amplifier circuit includes a MOS transistor connected between the output terminal and the second terminal; and a feedback circuit, including a resistor and a capacitor, having a low cut-off frequency which provides a bias voltage to the gate of the MOS transistor and forces the entire bias-current of the bias-current generator to flow through the MR element The arrangement is balanced with an additional MR element (optional), bias-current generator and amplifier circuit, which are substantially the same as the MR element, bias-current generator and amplifier circuit, respectively, with the cut-off capacitors of the two individual amplifiers being cross-coupled to reduce noise.

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Eindhoven, Netherlands

Joao N Ramalho