Ansys, Inc.

Clk Design Automation, Inc.

Joao Moreno Geada

Scott Johnson

Emrah Acar

Altan Odabasi

Qian Shen

Nicholas Lee Rethman

Norman H Chang

Sankar Ramachandran

Deqi Zhu

Lang Lin

Dinesh Kumar Selvakumaran

Murat R Becer

Ankur Gupta

Sudarsana Reddy Mallu

Anusha Gummana

Mirza Milan

Isadore T Katz

Tinu Thomas

Lee La France

Allen Baker

Ying-Shiun Li

Yaowei Jia

Shiva Raja

Hao Zhuang

Preeti Gupta

Youlin Liao

Nitin Kumar Pundir

Nick Rethman

Robert Geada

Arti Dwivedi

Suresh Kumar Mantena

Ganesh Tsavatapalli

Leon LaFrance

Ferenc Varadi

Ahran Dunsmoor

Rahul Rajan

James Kuzeja

Mathew Joseph Kaipanatu

According to one aspect of this disclosure, time domain information can be associated with switching probabilities and propagated through a simulated circuit during a static timing analysis to provide finer grain details for use by a power analysis of the simulated circuit (such as a dynamic voltage drop analysis or simulation). Signal correlations may also be propagated with the associated time domain information to provide further finer details for use in power analysis. A method according to one embodiment can include: determining, for each input pin of an aggressor element, a set of one or more time dependent input switching probabilities during a set of one or more corresponding timing windows in a simulated representation of a circuit; determining, from each time dependent input switching probability of each timing window, a set of time dependent output switching probabilities at an output pin of the aggressor element; and performing a power analysis for one or more victim circuit elements that are coupled to the aggressor element, the power analysis based on the set of time dependent output switching probabilities at the output pin of the aggressor element.

Timing domain based modeling of switching probability and signal correlation

Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.

Voltage impacts on delays for timing simulation

Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.

DVD simulation using microcircuits

Analysis of power supply noise in simulations of a design of a circuit can use per instance dynamic voltage drops (DVD) in timing analyses so that the simulated DVD values on a per victim cell basis can accurately guide the timing analysis on each victim instead of a global DVD for all victims during the timing analysis. In one embodiment, a method can: determine, during a power analysis simulation, a representation of an energy lost, during each switching window at each output of each victim cell, at one or more power supply rails of each of the victim cells in the set of victim cells due to aggressors in the design; and provide the representation of the energy lost separately for each victim cell to a timing analysis system. The representation can be a rectangle having a width defined by a switching window of a victim's output.

Dynamic voltage drop model for timing analysis

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die. Other methods, machine readable media and systems are also described.

Security information extraction and probe insertion for side-channel analysis

Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an iterative approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim. This approach can be both computationally efficient and accurate and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network.

Voltage drop analysis using local circuit representation

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

Register transfer level based side channel leakage assessment

Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit layout is received, the integrated circuit layout including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit layout based on a vulnerability characteristic of the vulnerable cell. A power analysis of a portion of the integrated circuit layout is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

Systems and methods for accurate voltage impact on integrated timing simulation

Techniques for computer aided design and engineering of integrated circuits can use group identifiers of correlated signals and time delay values when using vectorless dynamic voltage drop (DVD) simulations and when using other types of simulations or analyses of a circuit design. A method in one embodiment can include the operations of: receiving a design representing an electrical circuit that includes a plurality of pins, the plurality of pins including one or more input nodes or one or more output nodes in the electrical circuit; identifying, in the design, one or more groups of pins that are correlated such that, within each identified group, all of the pins in the identified groups switch between voltage states in a correlated way; assigning, for each pin in each identified group, an identifier for the identified group and a time delay value based on the pin's delay from an initial point in the identified group's logic chain to the pin. The group identifier and the time delay at each pin can limit the switching activities in the DVD simulations to reduce pessimistic results from the simulations. Other methods are described, and data processing systems and machine readable media that cause such systems to perform these methods are also described.

DVD analysis that accounts for delays

Example systems and methods are disclosed for performing a timing analysis on a circuit design. A plurality of switching scenarios are identified for the circuit design. One or more predictive models are applied to predict a subset of the plurality of switching scenarios that are likely to cause timing paths with critical timing problems. A dynamic voltage analysis is performed on timing paths based on the subset of switching scenarios. The one or more predictive models are applied to predict a set of critical timing paths based on the subset of switching scenarios that are likely to cause critical timing problems, the one or more predictive models taking into account the dynamic voltage analysis. A timing analysis is the performed on the set of critical timing paths.

Timing assistant for dynamic voltage drop impact on setup/hold constraints

This disclosure describes methods, systems and media for analyzing voltage drops in a power delivery network in a simulated design of an electrical circuit. In one embodiment, a system determines, for a victim element ('victim'), a voltage drop caused by each aggressor element ('aggressor') in a set of aggressors in the design and creates a data structure that includes, for each victim, at least one of: (1) each voltage drop caused by each aggressor in the set of aggressors or (2) a sum of the voltage drops on the victim caused by all of the aggressors in the set of aggressors. The system can then compute a set of simulations based on random inputs to generate a distribution of possible voltage drops for each victim using data in the data structure.

Dynamic voltage drop analysis with improved coverage

Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit design is received, the integrated circuit design including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit design based on a vulnerability metric of the vulnerable cell. A power analysis of a portion of the integrated circuit design is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

Growing community of inventors

Chelmsford, MA, United States of America

Joao Moreno Geada