Pragmatic Printing Limited

Pragmatic Semiconductor Limited

Joao De Oliveira

Richard John Price

Brian Hardy Cobb

Scott Darren White

Thomas Clark

Catherine Ramsdale

Richard Price

Neil Davies

Anthony Sou

Ken Williamson

Kenneth David Williamson

Pascaline Boulanger

Gillian Ewers

Rob Mann

Thomas Lee-Clark

An interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly includes a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within the flexible base layer, and at least one first patterned contact layer, provided on any one of the first surface and the second surface of the flexible base layer and which is configured to operably interface with the at least one active electronic circuit component and the at least one 1C component.

Flexible interposer

Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.

Measurement apparatus

An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.

And gates and clock dividers

A RFID (Radio Frequency Identification) system is provided, comprising at least one tag assembly having at least one tag inductance element that is operatively coupled to an integrated circuit (IC). The RFID system further comprises at least one reader assembly having at least one reader inductance element that is configured to operatively and communicatively couple with the tag assembly, and a resonance assembly having at least one first resonance element that is inductively coupleable to the at least one tag inductance element and/or at least one second resonance element that is inductively coupleable to the at least one reader inductance element, and which is adapted to provide coupled magnetic resonance signal transmission between the reader assembly and the tag assembly.

RFID system with improved signal transmission characteristics

An RFID tag for capacitively coupled RFID communication with an RFID reader. The RFID tag comprising an integrated circuit (IC), the IC including a first RFID tag electrode arranged to capacitively couple with a first electrode of the RFID reader to form a first capacitor, and a second RFID tag electrode arranged to capacitively couple with a second electrode of the RFID reader to form a second capacitor when the RFID tag is in a first position relative to the RFID reader; power supply circuitry configured to extract power from a first time-varying signal received from the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode, and supply the extracted power to circuitry of the RFID tag; and data transmission circuitry configured to receive the extracted power from the power supply circuitry, and transmit data to the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode.

Closed-system capacitive coupling RFID

AND gates and clock dividers

A system is disclosed, comprising a base and at least a first moveable entity, the first moveable entity being moveable with respect to the base and positionable in at least a first position with respect to the base. The base comprises a first base electrode and a second base electrode, and the moveable entity comprises a first moveable entity electrode and a second moveable entity electrode. The electrodes are arranged such that when the moveable entity is in the first position the first base electrode and the first moveable entity electrode align to form a first capacitor and the second base electrode and second moveable entity electrode align to form a second capacitor. The first moveable entity further comprises a first resistor connecting the first moveable entity electrode to the second moveable entity electrode, and the base further comprises: signal supply means arranged to supply a time-varying electrical signal to the first base electrode; and signal detection means arranged to detect an electrical signal from the second base electrode.

Capacitive detection, energy transfer, and/or data transfer system

A system is disclosed, comprising a base and at least a first moveable entity, the first moveable entity being moveable with respect to the base and positionable in at least a first position with respect to the base. The base comprises a first base electrode and a second base electrode, and the movable entity comprises a first moveable entity electrode and a second moveable entity electrode. The electrodes are arranged such that when the moveable entity is in the first position the first base electrode and the first moveable entity electrode align to form a first capacitor and the second base electrode and second moveable entity electrode align to form a second capacitor. The first moveable entity further comprises a first resistor connecting the first moveable entity electrode to the second moveable entity electrode, and the base further comprises: signal supply means arranged to supply a time-varying electrical signal to the first base electrode; and signal detection means arranged to detect an electrical signal from the second base electrode.

A comparator is disclosed, for comparing a first input voltage with a second input voltage and generating a corresponding output voltage. The comparator includes a follower stage coupled to a first supply rail and a second supply rail, a follower stage input terminal for the second input voltage, and a follower stage output terminal. The comparator also includes an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal for the first input voltage, and an inverter stage output terminal for providing an inverter stage output voltage having a first range. A signal conditioning means is coupled to the inverter stage output terminal and generates a comparator output voltage at a comparator output terminal having a second range larger than the first range.

Comparator

An antenna comprises: a first terminal; a second terminal; and a winding, having an inductance, comprising a plurality of turns and connected between the first and second terminals such that a change in magnetic flux linking the winding generates a corresponding voltage between said terminals. The winding comprises a conductive element connected to the first and second terminals and extending around said turns from the first terminal to the second terminal and having a thickness not exceeding X &#x3bc;m along a length of the conductive element from the first to the second terminal and a width not exceeding X &#x3bc;m along said length, where X is less than or equal to 10, whereby said conductive element is substantially non-visible to a naked human eye.

Antenna and apparatus comprising antenna

An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.

Growing community of inventors

Sedgefield, United Kingdom

Joao De Oliveira