U.S. Philips Corporation

Signetics

Joannes J Koomen

Roelof H Salters

Jan Lohstroh

Cornelis Maria Hart

Roger Cuppens

Marnix G Collet

Adrianus T Van Zanten

Cornelis D Hartgring

Cormac M O'Connell

In programmable memories of the EPROM or EEPROM type, a row and/or column of test memory cells are added to the matrix of rows and columns of non-volatile memory cells for the testing of the peripheral circuits which select and read the memory cells. The test memory cells have a very short write time as compared with the non-volatile memory cells and may be of the dynamic (or volatile) type. The write time for a memory cell of the EPROM or EEPROM may be, for example, 10 msec. The write time for a dynamic memory cell, however, is 100 nsec. The time required for testing the peripheral circuits can therefore be reduced by a factor of 80 (for a 16 Kbit memory) or higher (for memories larger than 16 Kbits).

Non-volatile, programmable semiconductor memory having reduced testing

An integrated logic circuit includes an output circuit for generating an output current which increases linearly in time. In integrated logic circuits the problem presents itself that the rapid variation of the (dis) charging of a data output causes a reverse voltage pulse VL across the inductance formed by the connection wires. The reverse voltage is limited by causing the charge or discharge current (for the load capacities present) to increase linearly to a maximum permissible value. This is done by driving the output field effect transistor with a control voltage VC which varies in time in the form of a square root.

Integrated logic circuit having a control circuit for generating a

A MOS power-on reset circuit includes Schmitt trigger circuit and an inverter. The Schmitt trigger circuit comprises first, second, and third depletion transistors serially connected between reference potential and supply voltage. The first and second depletion transistors are connected at a first junction point, and the second and third depletion transistors are connected at a second junction point. The gates of the first and second depletion transistors are commonly connected for receiving an input substrate bias voltage. An enhancement transistor is connected between the first junction point and supply voltage. The gates of the enhancement transistor and the third depletion transistor are commonly connected to the second junction point, which is the output of the Schmitt trigger circuit and which is coupled to the inverter from which the output voltage is taken. The transfer characteristic of the circuit exhibits hysteresis, with two trigger levels of input substrate bias voltage that differ sufficiently in magnitude that a triggering at one level, accompanied by a fluctuation in input voltage, will not cause a spurious triggering at the other level. Undesired oscillation of the circuit is thereby avoided.

MOS Power-on reset circuit

In a memory cell array of the kind including a memory cell capacitor and a memory cell transistor connected in series between a field plate line and a bit line, both the field plate line and bit line are precharged to the same potential level. The field plate line is connected to one input of a sense amplifier and the bit line is connected to the other input. The charge and discharge of the memory cell capacitor causes equal and opposite voltage changes on the field plate line and bit line. With respect to prior art the cell signal is increased by the amount of signal on the field plate line and when sensed against a reference signal which is about one-half the amount of the cell signal, the sensed signal is about twice that obtainable in the prior art.

Field plate sensing in single transistor, single capacitor MOS random

A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.

Self-aligned double polysilicon MOS fabrication

A simple MOS voltage divider uses three enhancement MOS transistors, which includes one load connected to two drivers in parallel. The gate of one driver is connected to the output node, and the other two gates are connected to the supply voltage. The transistors have a common substrate. By proper choice of the transistor geometry only, the output node voltage can be made independent of the threshold and temperature variations for output voltages larger than one threshold and smaller than one-half the supply voltage. Moreover, the ratio between the output and supply voltages remains constant.

MOS Voltage divider

The invention relates to a JFET memory in which the information at the gate electrodes of the JFET's is stored and read-out non-destructively. Each JFET has an IGFET structure situated entirely within the JFET and the gate of which is coupled to the source or drain of the JFET. The information can be refreshed periodically at cell level (that is without external amplifiers) by means of said IGFET.

Semiconductor memory device

A random access memory (RAM) in which each memory cell includes a JFET having two gate electrodes selectable by means of a single word line and a single bit line. The JFETs have a common electrode formed from the substrate of a semiconductor body common to each of the memory cells, which serves as one of the main electrodes of each of the JFETs.

Junction field effect transistor random access memory

JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary selection takes place on one of the main electrodes of the JFET structures in which the other main electrode can be connected to the supply. By means of a second common gate electrode the pinch-off voltage of the channels can be adjusted so that the channels are non-conductive in the non-selected condition and a good detection of the information state is obtained in the selected condition.

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Los Altos, CA, United States of America

Joannes J Koomen