Korg Incorporated

Joanne F Ottney

Alexander John Limberis

Joseph Watson Bryan

Steven S O'Connell

Marcus K Bryan, Jr

Steve S O'Connell

A sequence of instructions for a processor executing a plurality of real time programs is supplied from a memory having a set of memory locations. A controller is coupled to the memory for replacing a program with a replacement program. The controller disables writes in response to instructions in the sequence from a particular group of memory locations with idle or no-operation instructions in response to a command. A memory interface is coupled to the memory and to the controller through which new instructions for the replacement program are written to the particular group of locations. The technique is applied especially for audio signal processors with a need for dynamic replacement of active voice programs.

Code segment replacement apparatus and real time signal processor using

A processing system includes delay line management logic that automatically clears the delay lines without actually filling the delay line memory with zeroes. The processing system comprises a signal processor that executes programs using delay lines. A memory, coupled to the signal processor, includes a set of memory locations to store the delay lines. Delay line management logic is responsive to a command to automatically clear for the programs being executed by the signal processor a subset of the set of memory locations allocated to a particular delay line without writing to the subset of memory locations. The delay line management logic includes a register file to store parameters for the delay lines. The parameters for particular delay lines include an offset within the set of memory locations pointing to the subset of memory locations allocated to the particular delay line, and a count indicating the number of valid memory locations in the subset. The command to clear the delay line comprises an operation to update the register file by, for instance, setting the count for the particular delay line to zero.

Signal processor with delay line management logic

An architecture for a synthesizer of music or other sounds which comprises an input device which supplies real time input signals indicating selected voices, a voice program memory which stores voice programs for respective voices, and a sound processing module including an array of digital signal processors, which is coupled to the input device and the voice program memory, and responsive to real time input signals to execute a group of voice programs in the voice program memory to generate selective voices in real time. Resources coupled to the input device and the voice program memory dynamically assign voice programs for selected voices to the group of voice programs in response to the real time input signals. Further, resources are available for replacing a particular voice program in the group with a voice program for a selected voice in response to the real time input signals. The voice program memory includes a first memory which stores a plurality of voice programs, and a second memory which is coupled to the sound processing module and the first memory, which stores the group of voice programs for execution by the sound processing module. The resources for dynamically assigning a voice program to the group includes a system for transferring a selected voice program from the first memory to the second memory in real time. An audio output device, including a speaker, is coupled to the digital signal processor for producing sound in response to the sound data.

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Los Altos, CA, United States of America

Joanne F Ottney