Force10 Networks, Inc.

Joanna Lin

Glenn C Poole

Ann Gui

Heeloo Chung

Brad Danofsky

David Haddad

Krishnamurthy Subramanian

Joel R Goergen

An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Packet segmentation with different segment sizes for a switch fabric

A network packet is segmented for transfer through a switch fabric. The last segment of the packet is allowed to exceed the maximum size of previous segments so as to increase the switch fabric utilization. Other features are also provided.

Segmentation of network packets for a switch fabric

FIFO buffer with multiple stream packet segmentation

A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.

Dual signaling format switch fabric with multiplex capability

Growing community of inventors

San Jose, CA, United States of America

Joanna Lin