International Business Machines Corporation

Joachim Von Buttlar

Timothy John Slegel

Dan F Greiner

Kenneth J Oakes

Janet R Easton

Michel H T Hack

John S Trotter

Eberhard Engler

Martin Taubert

Andrew W Piechowski

Jonathan D Bradbury

Cedric Lichtenau

Laith M AlBarakat

Carsten Otte

Elke G Nass

Michel Hack

Martin Kuenzel

Joerg Kayser

Harald Boehm

Jens Mehler

Ambrose Verdibello

Robert M Whalen, Jr

Axel Horsch

Georg Drache

Sebastian Stork

Stefan Koerner

A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Clock comparator sign control

An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.

Exception summary for invalid values detected during instruction execution

A computer-implemented method for simulating a system of at least two computing systems connected via at least one data packet connection, wherein a computing system comprises interconnect adapters for physical connections based on a physical layer protocol each. A packet switching component is provided, as are physical attachments for each interconnect adapter. The physical attachments are registered. A connection director is provided for managing the data packet exchange. In response to the receipt of a simulation start indicator, each physical attachment registers its unique address at the package switching component. This assigns unique identifiers for each computing system, and unique identifiers for simulated physical layer protocols.

Simulating a system of computing systems

An instruction to convert data from a source data type to a target data type is obtained. The source data type is selected from one or more source data types supported by the instruction, and the target data type is selected from one or more target data types supported by the instruction. Based on a selected data type of the source data type or the target data type, a determination is made of a rounding mode for use by the instruction. The rounding mode is implicitly set based on the selected data type; it is assigned to the selected data type. A conversion of the data from the source data type to the target data type is performed. The conversion includes performing a rounding operation using the rounding mode implicitly set. The performing the conversion provides a result in the target data type, which is written to a select location.

Data conversion to/from selected data type with implied rounding mode

A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is '0' the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is '1', in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.

Rotate then operate on selected bits facility and instructions therefor

Rotate then operate on selected bits facility and instructions therefore

Disclosed are a method and system of tracking real time use of I/O control blocks on a processing unit basis, in a multiprocessing system, such that in the case of a processing unit failure, a list accurately and concisely identifies the control blocks that need to be recovered. This eliminates the need to scan all the I/O control blocks, greatly reducing the overall system recovery time and minimizing impact to the rest of the running system. The preferred embodiment of the invention uses a task control block structure to record which I/O control blocks are in use by each Processing Unit. Also, the lock word structure defined in the I/O control blocks is provided with an index back into the task control block to facilitate managing the task control block entries.

Method and system for state tracking and recovery in multiprocessing computing systems

Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.

Method and system to detect errors in computer systems by using state tracking

Disclosed is a method for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.

Method to detect errors in computer systems by using state tracking

A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured. Furthermore, the ongoing verification of the newly designed CPU using the method according to the present invention allows detection of problems with the processor hardware at a relatively early stage.

Method and system for testing a processor

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Schoenaich, Germany

Joachim Von Buttlar