Infineon Technologies Ag

Joachim Voelter

Joachim Mahler

Khalil Hosseini

Franz-Peter Kalz

Ralf Wombacher

A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Chip package and chip assembly

A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Growing community of inventors

Berlin, Germany

Joachim Voelter