Infineon Technologies Ag

Joachim Schnabel

Michael Hausmann

Bernd Klehn

Andre Schaefer

Helmut Fischer

Ralf Klein

Eckhard Brass

Martin Brox

Helmut Schneider

Michael Bernhard Sommer

Alexander Mayer

Johann Pfeiffer

Thoai-Thai Le

Thilo Schaffroth

J&uuml;rgen Lindolf

Andre Sch&auml;fer

Andrea Zuckerst&auml;tter

Sebastian Mosler

Xaver Obergrussberger

Kasimierz Szczypinski

Circuit arrangement, including a first resistor, a second resistor, a current source and an analog-to-digital converter. The second resistor is thermally coupled to the first resistor. The current source is coupled to the second resistor. The analog-to-digital converter is configured to receive a first voltage measured via the first resistor as a voltage to be digitized, and is configured to receive a second voltage measured via the second resistor as a reference voltage of the analog-to-digital converter.

Circuit arrangement and method for operating an analog-to-digital converter

A circuit for generating a refresh signal for a memory cell of a semiconductor memory includes a capacitor and a differential current source for providing a charging current to the capacitor. The differential current source includes a temperature-dependent and a temperature-independent current source connected such that the charging current is proportional to a difference between a temperature-dependent current and a temperature-independent current. A comparator a voltage at a capacitor terminal and a reference voltage. The comparator generates a refresh signal when capacitor voltage exceeds the reference voltage.

Differental current source for generating DRAM refresh signal

A method and circuit for refreshing dynamic memory cells arranged along word lines and bit lines are provided, the memory cells being refreshed in a manner dependent on a refresh signal with a refresh frequency by the activation of the word line in order to write the information back to the memory cells arranged on the relevant word line, in which case the refresh frequency is set in a manner dependent on the charge loss of first dummy memory cells during a refresh period of the refresh signal on a first dummy word line and/or in a manner dependent on the charge loss of second dummy memory cells during the refresh period of the refresh signal on a second dummy word line.

Method and regulating circuit for refreshing dynamic memory cells

The invention refers to a circuit device () with at least one connection (), to which a clock pulse (/CLK, /CLK) can be applied, whereby the circuit device () also comprises a clock pulse detection facility () for detecting whether there is a clock pulse (/CLK, /CLK) present at the connection (), or whether there is no clock pulse (/CLK, /CLK) present at the connection ().

Circuit device with clock pulse detection facility

An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at least one such arrangement of resistors, wherein the resistors, when viewed in a longitudinal direction of the resistors, are displaced in relation to one another.

Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement

An increased internal operating voltage for an integrated circuit can be generated with two two-stage charge pumps, ensuring reliable operation even in the event of an external voltage supply Vext=1.8 V or less. The two charge pumps cooperate with a common first stage in a cyclic sequence. A temporally offset organization of the cycles of the two charge pumps enables operation in a manner that is free from disturbances. Moreover, the large chip area required for capacitors can advantageously be considerably reduced.

Method of increasing an internal operating voltage for an integrated circuit, and integrated circuit

In a scalable driver device having a plurality of driver stages whose outputs are connected to a common terminal contact for providing a common output signal, drive parameters of the driver stages, individually or in groups, are so dimensioned that the difference of the edge rise times and/or fall times of the output signal from one active driver stage to the next driver stage to be activated is substantially equal to the difference of the edge rise times and/or fall times from a next activated driver stage to the one activated after that.

Scalable driver device and related integrated circuit

A circuit for generating a refresh signal for a memory cell, includes a temperature-independent current source, a temperature-independent voltage source, and a temperature-dependent reference voltage source. A capacitor's first and second terminals are connected respectively to the temperature-independent current source, and the temperature-independent voltage source. The capacitor's first terminal is connected to a first input terminal of a comparator. The comparator's second input is connected to the temperature-dependent reference voltage source. The comparator is configured to output a refresh signal in response to a difference between voltages present at the first and second inputs thereof.

Temperature-dependent refresh cycle for DRAM

Signal generator for charge pump in an integrated circuit

Limiter for refresh signal period in DRAM

A method for driving a plurality of circuit units to be controlled includes applying a control signal to a control signal connection unit and an activation signal to an activation connection unit. A hold signal is the generated on the in response to the activation signal. This hold signal is combined with the control signal to obtain a modified control signal, which is then made available at an output.

Control signal generating device for driving a plurality of circuit units

A circuit has a control signal input, a control signal output, a delay element for generating a delay duration, and a control logic circuit. The latter controls the delay element and switches a change in the state at the control signal input to the control signal output in a manner delayed by the delay element, if a minimum time interval between state changes at the control signal input is undershot. The circuit is employed in DRAMs for controlling the active times of the voltage generators present in DRAMs.

Drive circuit and control method

Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Programmable voltage pump having a ground option

A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or falling edge with a different gradient. The output signals of the level converters are combined in a logic combination element. The logic combination element drives a togglable storage element, which provides the level-converted output signal. The duty ratio of the input signal is not changed during the level conversion, independently of production-dictated variations in the component parameters.

Logic signal level converter circuit and memory data output buffer using the same

An integrated memory has a memory cell array with row lines and column lines. A row decoder for activating row lines is connected to address lines for transferring address signals. A voltage regulating circuit serves for applying a regulatable supply voltage to one of the row lines. For the purpose of setting the supply voltage, a driving circuit is connected to the address lines and to the voltage regulating circuit. This enables trimming of the voltage regulating circuit in conjunction with a comparatively small area requirement.

Growing community of inventors

Munich, Germany

Joachim Schnabel