Micronas Gmbh

Tdk-Micronas Gmbh

Trident Microsystems (Far East) Ltd.

Joachim Ritter

Joerg Franke

Reiner Bidenbach

David Muthers

Thomas Kauter

Wolfgang Horn

Thilo Rubehn

Jörg Franke

Dieter Baecher

Gert Umbach

Dieter Bächer

Steffen Zimmermann

Christian Jung

Peter Möller

Michael Wagner

Zoran Mijovic

Markus Von Ehr

Manfred Jünke

Franke Jörg

A sensor unit for detecting an encoder at a predefined position, having a circuit device and a threshold signal present at the circuit device, and a magnetic field sensor. The magnetic field sensor has a supply and ground terminal and first and second outputs, and outputs an analog sensor signal that is dependent on the distance of the encoder, and a supply unit connected to the supply terminal of the magnetic field sensor, the supply unit having a control input, and the circuit device is connected to the magnetic field sensor. The circuit device is configured to provide the sensor signal as an amplified signal value, and the circuit device is configured to determine an amount from the difference between the amplified signal value and the threshold signal and to control the amplification of the signal value and the supply unit as a function of the magnitude of the amount.

Sensor unit and method for detecting an encoder at a predefined position

An arrangement for testing integrated circuits includes an integrated test circuit and a cluster which has at least one integrated circuit and a second integrated circuit. The first integrated circuit is provided in a first component region of a wafer, and the second integrated circuit in a second component region. The first component region and the second component region are spaced a distance apart by a scribe line of the wafer. The integrated test circuit is connected to the first integrated circuit via a first test line section, and the second integrated circuit is connected to the first test line section via a first connecting line that has a first well in the semiconductor material, the first well extending continuously in the wafer from the first component region over the scribe line to the second component region, the first well being electrically insulated from a substrate of the wafer.

Arrangement for testing integrated circuits

A method is provided for operating a magnetic field detector circuit, whereby the magnetic field detector circuit is operated alternately in an active state or in a sleep state and the magnetic field detector circuit has a magnetic field measuring device and a wake-up timer, whereby the magnetic field measuring device comprises a magnetic field sensor. In the active state, the magnetic field measuring device is operated with a supply voltage and an output signal is generated by the magnetic field sensor. The magnetic field detector circuit comprises a wake-up timer, whereby the wake-up timer is operated with the supply voltage in the sleep state and a wake-up signal is generated by the wake-up timer after a predetermined sleep interval, and the magnetic field measuring device changes from the sleep state to the active state.

Method for operating a magnetic field detector circuit and a magnetic field detector circuit

A method for testing a signal path of a first IC formed as a monolithically integrated circuit on a semiconductor body together with a magnetic field sensor and has a signal output and a power supply connection and a test mode state and a normal operating state. A power supply of the first IC is switched off, and a signal output is connected with a reference potential, and the power supply of the first IC is switched on and the signal output is disconnected from the reference potential. Subsequently in a test mode state, a self-test is performed in the first IC and a test pattern is configured at the signal output or at the power supply connection and the test pattern is evaluated by the control unit for testing of the signal path.

Method for testing a signal path

A measuring system having a first magnetic field sensor, a second magnetic field sensor, a third magnetic field sensor, an encoder, and an evaluation circuit to which the first magnetic field sensor, the second magnetic field sensor, and the third magnetic field sensor are connected. The evaluation circuit is configured to determine the position of the encoder based on a first measurement signal of the first magnetic field sensor and a second measurement signal of the second magnetic field sensor and a third measurement signal of the third magnetic field sensor.

Measuring system

A measuring system having a first magnetic field sensor, an encoder, and an evaluation circuit. The first magnetic field sensor and the second magnetic field sensor and the third magnetic field sensor are connected to the encoder. The evaluation circuit has a logic, which is set up to determine the position of the encoder based on a first measurement signal of a first magnetic field sensor and a second measurement signal of a second magnetic field sensor and a third measurement signal of a third magnetic field sensor.

A measuring system having a first magnetic field sensor, a second magnetic field sensor, an encoder, and an evaluation circuit to which the first magnetic field sensor and the second magnetic field sensor are connected. The evaluation circuit generates a first signal and a second measurement signal. The encoder generates a second magnetic field change with a second periodicity. The evaluation circuit generates a second signal with the second periodicity from the first measurement signal of the first magnetic field sensor and the second measurement signal of the second magnetic field sensor according to an absolute value function.

Circuit and measuring system

The invention relates to an integrated circuit arrangement with connection contacts for the serial exchange of data and/or signals with external components and apparatuses and with a control apparatus and/or a serial interface for the clocked receiving of data by means of a signal voltage on such a connection contact, which voltage is modulated between at least one low, one middle and one high voltage state. The control apparatus and/or the interface are designed in such a manner that data is sent in a sending mode via the connection contact in that the switching apparatus, after having received a slope changing in particular from the middle voltage state into in particular the higher or the lower voltage state, pulls the voltage state into the in particular opposite lower or higher voltage state. Furthermore, the invention relates to an apparatus and a process for operating such a circuit arrangement.

Circuit arrangement, apparatus and process for the serial sending of data via a connection contact

A monolithic sensor arrangement includes a housing, a sensor integrated in the housing, and two or three connecting contacts deployed on the housing so as to provide a contact with the sensor. The housing also includes an integrated digital circuit includes a freely programmable digital processor, a program memory and a data memory, which are used to control and/or process the functionalities and/or the measured data of the sensor.

Monolithic sensor arrangement and method for controlling a monolithic sensor arrangement

An integrated circuit for an asynchronous serial data transfer comprises a sampler to sample the asynchronous serial data using a sampling clock. A bit length counter determines a bit time by counting a number (m) of predetermined clock cycles, where the bit length terminal variably adjusts the number (m) of clock cycles of the bit length counter.

Integrated circuit for an asynchronous serial data transfer with a bit length counter

The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C, C) for data and/or signal exchange with external components and setups. At one of the terminals (C), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V, V) that can be controlled and which are different from a supply voltage level (V) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.

Circuit configuration with serial test interface or serial test operating-mode procedure

A memory device containing data to be protected is integrated with a microprocessor and includes a first and a second memory portion with different accessibilities. The integration of the memory device on the same integrated circuit (IC) or chip as the microprocessor permits a combination of protective hardware and software measures that are not possible with a memory device that is on a different IC than the microprocessor. The first memory portion holds an initialization program that also serves as a boot program during decryption, and the second memory portion holds a user program, for example, a program for decrypting and/or decoding received data. Such data may be, for example, audio data encoded according to the MP3 standard and encrypted with a secret or public password against unauthorized reception.

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Loerrach, Germany

Joachim Ritter