Agilent Technologies, Inc.

Hewlett-packard Company

Verigy (singapore) Pte. Ltd.

Joachim Moll

Marcus Mueller

Markus Rottacker

Martin Muecke

Thomas Burger

Martin Heinen

Michael Fleischer-Reumann

Guenter Tietz

Heiko Schmitt

The invention refers to analyzing a digitally modulated test signal received from a device under test -DUT-, comprising providing a first sampled signal by assigning a first sequence of digital values as result of a level comparison of the test signal with a first threshold at first successive timing points, generating a first masking signal indicating matches between a second sequence of digital values expected from the DUT and one or a plurality of first data patterns, and analyzing the first sampled signal in conjunction with the masking signal.

Digital signal analysis with evaluation of selected signal bits

An integrated circuit (), preferably a field programmable gate array&#x2014;FPGA or an application specific integrated circuit&#x2014;ASIC&#x2014;, comprises a level comparator () for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit () is coupled to the level comparator () for sampling (SAM) the comparator output signal (COS). A bit error test unit () receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

Integrated circuit with bit error test capability

For testing a digital data signal, a value derived from the digital data signal at a sampling point is compared against a corresponding value of an arbitrary test signal. The comparison is interpreted as an error in case the derived value does not substantially match with the corresponding value of the arbitrary test signal.

Digital data signal testing using arbitrary test signal

Determining a jitter property of a signal with a repetitive bit sequence of a plurality of bits includes setting a sample point at a first sampling position relative to a first transition within the bit pattern, assigning a set of digital values to comparison results of the digital signal with a threshold at the set sample point for a plurality of repetitions of the bit sequence, determining a distribution value on the base of the sum of the assigned digital values, shifting the sample point by a time increment, iteratively repeating determining the distribution value until the sample point has reached a second sampling position, determining from the distribution values a distribution function over the sample points, and determining the jitter property by using the distribution function.

Determination of a jitter property of a signal

Testing a device under test&#x2014;DUT&#x2014;includes providing a test signal from the DUT to a test probe, taking from the test signal being present at the test probe analog samples at a first sampling rate, taking from the test signal being present at the test probe digital samples at a second sampling rate, providing a control signal indicative of sampling times of the analog samples, and performing an analysis of the digital samples in conjunction with the control signal.

Performing a signal analysis based on digital samples in conjunction with analog samples

A noise signal generator includes a random word generator for generating a sequence of random words, each word representing an input value, a mapping unit for receiving the sequence of random words, mapping each input value to an output value of according to a probability distribution function, and providing a corresponding sequence of output values, and a digital-to-analog converter for generating a noise signal based on the output values.

Noise signal generation by mapping random words

A coupling unit that couples at least two pins of an ATE (Automated Test Equipment) to a pin of a device under test includes an ATE interface for receiving a plurality of first stimulus signals from selected ATE-pins and/or for sending a plurality of first response signals to the selected ATE-pins, a DUT interface for sending a second stimulus signal to the DUT-pin and/or for receiving a second response signal from the DUT-pin, and a multiplexer circuit for serializing data of the plurality of first stimulus signals into the second stimulus signal and/or a de-multiplexer circuit adapted for parallelizing data of the second response signal into the plurality of first response signals.

Pin coupler for an integrated circuit tester

A signal-analyzing unit has a sampling path and a reference path both receiving a digital test signal. The sampling path has a first comparator for comparing the test signal against a first threshold value and providing a first comparison signal, and a first sampling device receiving as input the first comparison signal and a first timing signal. The reference path has a second comparator for comparing the test signal against a second threshold value and providing a second comparison signal, and a second sampling device for receiving as input the second comparison signal and a second timing signal. An analysis unit receives and analyzes the output of the sampling and reference paths.

Signal sampling with sampling and reference paths

A delay unit for providing an output signal delayed by a delay time with respect to a periodic signal received at its input, the delay unit comprises a first delay cell adapted to receive the periodic signal and to provide as output a first delayed signal corresponding to the input periodic signal but delayed by a variable first delay time. A selection unit receives the first delayed signal and a second signal derived from the periodic signal. A control unit controls the selection unit in order to select one of the first delayed signal and the second signal as the output signal of the delay unit, and further controls the first delay time of the first delay cell.

Delay unit for periodic signals

A frequency-providing circuit is disclosed for providing an output signal at a frequency f,. The circuit comprises a frequency-generating unit, a frequency-changing circuit, and a synchronizing circuit. The frequency-generating unit receives a frequency-selecting control signal and provides a frequency output at a frequency f,, whereby the frequency-generating unit is switchable between different frequencies substantially without a settling time. The frequency-changing circuit receives the frequency output and a frequency-changing control signal and derives the output signal therefrom, whereby the frequency f,of the output signal can be changed, with respect to the frequency f,, in accordance with the setting of the frequency-changing control signal. The synchronizing circuit synchronizes the frequency-selecting control signal and the frequency-changing control signal.

Frequency-providing circuit

Described is a variable digital delay cell with a first input for receiving a first input signal to be delayed, a first output for providing a first output signal which is delayed with respect to the first input signal, and a control signal for controlling the delay time of the delay cell. The delay cell further includes a second input for receiving a second input signal which is delayed with respect to the first input signal, and a second output for providing a second output signal which is delayed with respect to the first input signal by a fixed delay time. The delay cell according to the invention can be driven as a single device, but also allows a cascading of an `unlimited` number of delay cells without increasing the base delay in comparison to a single delay cell.

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Herrenberg, Germany

Joachim Moll