Infineon Technologies Ag

Infineon Technologies Austria Ag

Joachim Mahler

Khalil Hosseini

Michael Bauer

Manfred Mengel

Edward Fuergut

Alfred Haimerl

Ivan Nikitin

Angela Kessler

Wolfgang Schober

Stefan Landau

Georg Meyer-Berg

Anton Prueckl

Ralf Otremba

Henrik Ewe

Reimund Engl

Franz-Peter Kalz

Josef Hoeglauer

Hans-Joachim Schulze

Thomas Behrens

Ralf Wombacher

Horst Theuss

Heinrich Koerner

Werner Kanert

Michael Huettinger

Brigitte Ruehle

Johannes Georg Laven

Klaus Schiess

Swee Kah Lee

Peter Strobel

Soon Lock Goh

Alexander Heinrich

Guenther Ruhl

Jochen Dangelmaier

Edmund Riedl

Johannes Lodermeyer

Francisco Javier Santos Rodriguez

Xaver Schloegel

Markus Brunnbauer

Bernhard Winkler

Thomas Basler

Frank Hille

Antonio Vellei

Frank Daeche

Johann Gatterbauer

Konrad Roesl

Bernd Betz

Sook Woon Chan

Ivan Galesic

Anton Mauder

Matthias Stecher

Hans-Joerg Timme

Chau Fatt Chiang

Thomas Bemmerl

Juergen Schredl

Stefan Paulus

Kok Yau Chua

Erwin Huber

Thomas Laska

Daniel Pedone

Mei Chin Ng

Bernd Rakow

Beng Keh See

Thorsten Meyer

Markus Zundel

Gottfried Beer

Petteri Palm

Manfred Engelhardt

Peter Irsigler

Manfred Schneegans

Rainald Sander

Carsten Von Koblinski

Thomas Fischer

Irmgard Escher-Poeppel

Christian Jaeger

Gerhard Noebauer

Stephan Voss

Hermann Gruber

Christian Fachmann

Dominic Maier

Erich Griebl

Mathias Vaupel

Joachim Krumrey

Uwe Hoeckele

Daniel Porwol

Uwe Kirchner

Wolfram Hable

Rainer Steiner

Wae Chet Yong

Josef Höglauer

Wolfgang Scholz

Werner Kroeninger

Stanley Job Doraisamy

Oliver Eichinger

Philipp Seng

Michael Juerss

Peter Tuerkes

Frank Kahlmann

Reinhard Pufall

Andreas Schloegl

Steffen Jordan

A method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Chip package, method of forming a chip package and method of forming an electrical contact

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

Semiconductor device with a heterogeneous solder joint and method for fabricating the same

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.

Die attach methods and semiconductor devices manufactured based on such methods

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.

Manufacturing a package using plateable encapsulant

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Method of forming an electrical contact and method of forming a chip package with a metal contact structure and protective layer

A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.

Chip package with cross-linked thermoplastic dielectric

A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.

A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

Metallic interconnect, a method of manufacturing a metallic interconnect, a semiconductor arrangement and a method of manufacturing a semiconductor arrangement

In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

Method for forming a chip package with compounds to improve the durability and performance of metal contact structures in the chip package

Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.

Temperature sensor

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

Chip package comprising a chemical compound and a method of forming a chip package comprising a chemical compound

A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.

Power semiconductor devices and a method for forming a power semiconductor device

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Chip package and method of forming a chip package with a metal contact structure and protective layer, and method of forming an electrical contact

A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.

Semiconductor device including a heat sink structure

Growing community of inventors

Wuppertal, Germany

Joachim Mahler