Infineon Technologies Austria Ag

Infineon Technologies Ag

Joachim Krumrey

Walter Rieger

Franz Hirler

Martin Poelzl

Oliver Haeberlen

Ralf Henninger

Ralf Siemieniec

Gerhard Noebauer

Lutz Goergens

Johannes Schoiswohl

Markus Zundel

Oliver Blank

Martin Henning Vielemeyer

Maximilian Roesch

Rudolf Zelsacher

Uli Hiller

Andrew Wood

Jan Ropohl

Marc Probst

Martin Pölzl

Milko Paolucci

Mathias Born

Joachim Mahler

Jenoe Tihanyi

Khalil Hosseini

Wolfgang Werner

Heimo Hofer

Christian Foerster

Oliver Haeberlein

Sonja Krumrey, Legal Representative

Martin P&ouml;lzl

A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

Power MOSFET semiconductor

A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.

Monolithic semiconductor switches and method for manufacturing

A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.

Method and device including transistor component having a field electrode

Power MOSFET semiconductor device

A connection element is arranged on a connection area of a semiconductor component. The connection element includes at least one bonding wire portion fixed on the connection area. The connection area is covered by an electrically conductive material, the fixed bonding wire portion being surrounded or embedded by the electrically conductive material.

Connection element for a semiconductor component and method for producing the same

In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material.

Semiconductor device

One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.

Semiconductor device with trench field plate including first and second semiconductor materials

One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.

The application relates to a semiconductor device made of silicon with regionally reduced band gap and a process for the production of same. One embodiment provides a semiconductor device including a body zone, a drain zone and a source zone. A gate extends between the source zone and the drain zone. A reduced band gap region is provided in a region of the body zone, made of at least ternary compound semiconductor material.

Semiconductor device with a reduced band gap and process

A method for producing an integrated circuit including a semiconductor and in one embodiment a trench transistor structure, is disclosed. A first diffusion method is carried out. A second diffusion method is carried out, by which dopant atoms of a second conduction type are introduced via a first side into a mesa region and into a component region, which form a source zone in the mesa region, the diffusion methods being coordinated with one another in such a way that the dopant atoms of a second conduction type indiffuse further than the dopant atoms of a first conduction type from the first diffusion method, in the vertical direction in the component region and indiffuse not as far as the dopant atoms of the first conduction type in the vertical direction in the mesa region.

Method for producing an integrated circuit with a trench transistor structure

Growing community of inventors

Goedersdorf, Austria

Joachim Krumrey