Freescale Semiconductor,inc.

Other

Nxp Usa, Inc.

Motorola Corporation

Joachim Kruecken

John M Pigott

Peter Hans Schulmeyer

Jerome Romain Enjalbert

Thomas Henry Luedeke

Florian Bogenberger

Markus Baumeister

Christopher Temple

Rolf Dieter Schlagenhaft

Jalal Ouaddah

A voltage regulator for digital loads combines a closed loop regulation circuit with an open loop topology. A transistor and a bank of transistors share the same voltage source VDD and gate control current. Each of the bank of transistors is sized to match different current load requirements and one or more may be switched in or out as appropriate when the digital load transitions from one operating mode to another. The regulator has good DC load regulation and unconditional stability regardless of output capacitance.

Voltage regulator, application-specific integrated circuit and method for providing a load with a regulated voltage

A method of processing data comprising performing a sequence of operation instructions with variable operand size, wherein respective size codes for different source and destination operands are obtained and registered separately from performing the sequence of operation instructions, and the sequence of operation instructions is performed using operand sizes defined by the registered size codes, the operation instructions of the sequence not themselves containing size codes.

Data processing with variable operand size

An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.

Electronic circuit, safety critical system, and method for providing a reset signal

A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.

Data processing system, data processing method, and apparatus

A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay.

Clock glitch detection

An electronic device comprises a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory. The processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency. A second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit.

Electronic device having a memory element and method of operation therefor

A method and apparatus for assigning unique addresses to each generic &ldquo;node&rdquo; in a distributed control system that contains a main controller ( ) coupled to a plurality of generic nodes ( ) via a distributed communication bus ( ). The main controller ( ) provides currents and/or voltages to the communication bus ( ) via a supply ( ). In one embodiment, each node ( ) processes the current and voltages to store reference voltages and distance voltages proportional to its distance along the communication bus ( ). In another embodiment, each node ( ) signals to the main controller ( ) when the distance voltage reaches a certain value relative to the reference voltage. The main controller ( ) processes the arrival times of these signals to determine a relative distance to each node ( ). This distance information is used to assign a unique address to each generic node ( ) for identification during normal mode of operation.

System for address initialization of generic nodes in a distributed command and control system and method therefor

A method and apparatus for assigning unique addresses to each generic 'node' in a distributed control system that contains a main controller (52) coupled to a plurality of generic nodes (54) via a distributed communication bus (55). The main controller (52) provides currents and/or voltages to the communication bus (55) via a supply (58). In one embodiment, each node (54) processes the current and voltages to store reference voltages and distance voltages proportional to its distance along the communication bus (55). In another embodiment, each node (54) signals to the main controller (52) when the distance voltage reaches a certain value relative to the reference voltage. The main controller (52) processes the arrival times of these signals to determine a relative distance to each node (54). This distance information is used to assign a unique address to each generic node (54) for identification during normal mode of operation.

Growing community of inventors

Munich, Germany

Joachim Kruecken