Itt Industries, Inc.

Joachim Grosse

Arnold Uhlenhoff

Wolfgang Gollinger

Dieter Holzmann

Wilfried W Gehrig

The ternary-binary conversion is reached by two CMOS inverters dimensioned extremely unsymmetrically with regard to their W/L ratio and connected in parallel at their inputs. By further addition of a NAND or a NOR gate the circuit can be used in an integrated circuit as option releasing stage without additional terminal for the option signal which has only to be chosen as the middle value of the ternary signal whereas its lower and upper values are the binary signals.

CMOS Circuit for converting a ternary signal into two binary signals,

A keyboard switch matrix has a plurality of column and row wires and switches having only two poles and no interconnecting diodes for selectively connecting one of said columns to one of said rows. Associated with each column and row wire is a flip-flop having a set input connected to the wire and an electronic switch for each flip-flop connecting a flip-flop output to the set input. The outputs of the row flip-flops are connected to a NOR-gate, the output of which is connected to a control input of the electronic switches associated with the column flip-flops and also to a second set input of the column flip-flops. The output of the NOR-gate is further connected to a control input of the electronic switches associated with the row flip-flops through an inverter. Reset inputs of the column flip-flops are connected to the NOR-gate output through a differentiation circuit which is triggered by a negative pulse edge. A second NOR-gate has its inputs connected to the column wires and provides an output to a differentiation circuit which is triggered by a positive pulse edge. The output of the differentiation circuit is connected to reset inputs of the row flip-flops. Thus, the geometric position of the actuated keyboard switch is stored in the respective row and column flip-flops, and code signals corresponding to said position are provided at the outputs of said flip-flops.

Circuit arrangement for an input keyboard

A circuit arrangement for generating a pulse train having a predetermined first pulse spacing (a) and a second pulse spacing (b) differing from the first by an integral factor greater than one, which pulse spacings are assigned to the binary ZERO and the binary ONE, respectively, dependent upon a predetermined n-bit binary word.

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Breisach-Gundlingen, Germany

Joachim Grosse