Sun Microsystems, Inc.

Jo C Ebergen

Ivan E Sutherland

Robert J Drost

Robert David Hopkins

William Stuart Coates

Ian W Jones

Bernard Tourancheau

George J Chen

Justin M Schauer

Stephen Byram Furber

One embodiment of the present invention provides a system that asynchronously controls sending data items from a sender to a receiver. This system includes a set of sending FIFOs, a set of receiving FIFOs, as well as a shared data path between the sender and the receiver. The system also includes a set of control paths that operate in parallel between the sender and the receiver, wherein a given control path controls the transmission of data items between a corresponding sending FIFO and a corresponding receiving FIFO through the shared data path. The system further includes a round-robin scheduling mechanism which activates one control path at a time in a predetermined sequence. An activated control path asynchronously controls the sending of a data item from a corresponding sending FIFO to a corresponding receiving FIFO. By operating the control paths in parallel in the predetermined sequence, the system does not have to wait a request-acknowledge cycle time between the sender and the receiver before sending consecutive data items through the shared data path, but can instead send multiple data items through the shared data path within a single request-acknowledge cycle time.

Apparatus and method for high-throughput asynchronous communication with flow control

A pulse circuit contains an input stage configured to receive input pulses on input nodes using push-pull elements, wherein a given push-pull element is configured to receive an input pulse on a given input node and to provide a corresponding internal signal. The pulse circuit further contains a feedback loop that includes a logic element coupled between outputs from the push-pull elements and reset nodes of the push-pull elements. This logic element is configured to provide one or more outputs from the pulse circuit and to reset the internal signals from the push-pull elements via the feedback loop.

Pulse-signaling circuits for networks on chip

One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter. Next, the system generates objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort. The system then uses the objective functions to generate a constraint expression, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter. Next, the system computes a trade-off curve using the constraint expression. The system then computes transistor sizes for the circuit path based on a selected point from the trade-off curve.

Performing a constrained optimization to determine circuit parameters

One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling circuit for the asynchronous circuit from a source external to the asynchronous circuit. The system then uses the clock signal to limit the maximum repetition rate of the asynchronous circuit so that only a predetermined number of asynchronous transactions may take place during each cycle of the clock signal.

Method and apparatus for limiting the number of asynchronous events that occur during a clock cycle

One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.

Arbiters with preferential enables for asynchronous circuits

One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit contains a pipeline comprised of a number of stages of domino logic, including a present stage that receives one or more inputs from a prior stage and that generates one or more outputs for a next stage. The present stage includes a control circuit that is configured to ensure that the present stage enters a precharging state before entering an evaluation state&mdash;in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit operates by receiving a prior control signal from the prior stage and sending a present control signal to the next stage. During this process, the control circuit ensures that a minimum cycle time between successive evaluation states is six gate delays.

Growing community of inventors

San Francisco, CA, United States of America

Jo C Ebergen