Micron Technology Incorporated

Jiyun Li

Nathaniel J Meier

Timothy B Cowles

Yuan He

Michael Amiel Shore

Dennis G Montierth

Scott James Derner

Dean D Gans

Randall J Rooney

Matthew D Jenkinson

Daniel B Penney

Christopher John Kawamura

Tae Hyoung Kim

Jason M Brown

Beau D Barry

Adam J Grenzebach

Charles L Ingalls

Christopher Gordon Wieduwilt

Boon Hor Lam

Toby D Robbs

Shawn M Hilde

Greg S Hendrix

Christopher J Kawamura

Johnathan L Gossi

Eric J Rich-Plotkin

Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

Integrated assemblies having voltage sources coupled to shields and/or plate electrodes through capacitors

Methods, systems, and devices for circuit for tracking access occurrences are described. For instance, a memory device may include a memory array with column lines extending in a first direction and row lines extending in a second direction. The memory device may include a set of sense amplifiers adjacent to the memory array in the first direction, where a first subset of the set of sense amplifiers is coupled with the first set of column lines and a second subset of the set of sense amplifiers is coupled with the second set of column lines. The memory device may include a circuit adjacent to the set of sense amplifiers along the second direction, where the circuit is configured to increment, based on the access operation for the row line, a value including the logic states read by the second subset of the set of sense amplifiers.

Circuit for tracking access occurrences

Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Methods for row hammer mitigation and memory devices and systems employing the same

Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.

Multi-level cells, and related arrays, devices, systems, and methods

Apparatuses, systems, and methods for compensated sense amplifier with cross-coupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.

Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors

Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.

Apparatuses and methods for single-ended sense amplifiers

Some embodiments include an integrated assembly having a memory array over a base. The memory array includes a three-dimensional arrangement of memory cells. Sense amplifiers are associated with the base and are directly under the memory array. Vertically-extending digit lines pass through the arrangement of the memory cells and are coupled with the sense amplifiers. Some embodiments include an integrated assembly having a memory bank containing 64 memory chunks arranged in a 16×4 configuration. Some embodiments include an integrated assembly having a memory bank which contains 512 megabytes divided amongst 64 memory chunks which each have 8 megabytes. The 64 memory chunks are arranged in a configuration having multiple rows which each contain a two or more of the memory chunks.

3D DRAM with multiple memory tiers and vertically extending digit lines

The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is 'victimized.' When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

Apparatuses and methods for tracking victim rows

An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Apparatuses and methods for controlling steal rates

A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.

Systems, devices, and methods for efficient usage of IO section breaks in memory devices

Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.

Apparatus with latch correction mechanism and methods for operating the same

Some embodiments include an integrated assembly having a memory deck over a base, and having an array of memory cells along the memory deck. The array includes rows which extend along a row direction and columns which extend along a column direction. Wordlines are along the rows and digit-lines are along the columns. CONTROL circuitry is along the base and includes WORDLINE DRIVER circuitry coupled with the wordlines. The CONTROL circuitry is subdivided amongst banks. The banks are elongated along the row direction. Each of the banks is subdivided amongst a series of sections, with the sections being arranged in section rows which extend along the row direction. Each of the sections includes a series of patches, with the patches including INPUT/OUTPUT circuitry. The patches are arranged in groups, with the groups sharing portions of the WORDLINE DRIVER circuitry.

Integrated assemblies

Methods, systems, and devices for a compression method for defect visibility in a memory device are described. A memory device may identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with the first set of memory cells. The memory device may generate an indication of a location of the one or more errors in the first set of memory cells and compress the first set of data to generate an error flag based on identifying the one or more errors. The memory device may output the error flag and the indication of the location based on generating the error flag and the indication.

Growing community of inventors

Boise, ID, United States of America

Jiyun Li