Samsung Electronics Co., Ltd.

Jiyong Lee

Cholmin Kim

Kwanghee Lee

Deokho Seo

Jongmin Park

A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

Semiconductor memory device for hash solution and method of driving the same

A host device controls a storage device to perform a read operation of a read data unit with respect to selected memory areas. A read latency corresponding to the read operation of the storage device is stored in a read latency table of the host device. A determination is made whether a latency change ratio exceeds a threshold value, based on the read latency stored in the read latency table. The data host requests a data retention operation from the storage device, through a retention command, when the latency change ratio exceeds the threshold value.

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Anyang-si, South Korea

Jiyong Lee